Search:

Type: Posts; User: TrickyDicky

Page 1 of 20 1 2 3 4

Search: Search took 0.06 seconds.

  1. Closed: Re: Good verilog or vHDL book for implementation of mathematical operations

    Most books around are several years old. Technology moves on. You can get good performance from good RTL code without having to hand place or any optimised LUT or DSP design. Inference is pretty good.
  2. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    I agree with ads-ee. You should be able to read all the data into an array in zero time. I would usually do this in an initiallisation function rather than a process. If you are relying on the 1ns...
  3. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    I dont quite know what you mean? A ROM in an FPGA is just a BRAM/M9k whatever thats pre-loaded with data with the write-port not connected. This can be infered from HDL as a constant with synchronous...
  4. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    The problem is you're trying to create an array before you know the size. So if you need to read the whole file into an array you can do one of the following:
    1. Read the file to see how big it is,...
  5. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    You should not create a type from a signal. Your array is only length 1 (0 downto 0). You should use some constant value to set the length of the type
  6. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    you can call a function during initiialisation:


    function some_init_func return integer is
    begin
    return 10;
    end function;

    constant SOME_CONSTANT : integer := some_init_func;
    signal...
  7. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    What do you mean by "doesnt seem to open"? Does it throw an error about the file not existing? Is there no stimulus? Please explain the problem or show the error.
  8. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    array is a reserved word for the creation of a type. So it cannot be used as an object name.
  9. Closed: Re: What is the future of Boolean algebra-based languages and methodologies?

    Possibly, but nothing that is public afaik.
    Remember any radical change is not going to be bought, and there wont be any experience with it. Its a chicken and egg problem.
  10. Closed: Re: What is the future of Boolean algebra-based languages and methodologies?

    Intel are struggling with their 14 and 10nm chip fab. They have stuff to market now they were trailing 4 years ago and its about 2-3 years later than planned. They are going after the server market....
  11. Closed: Re: Problem calling a function from my vhdl project in Vivado.

    The best rule for converting to VHDL is to understand the code and re-write in VHDL. Direct port is always going to be a mess

    That error is because you're using VHDL 2008 syntax. The Vivado...
  12. Closed: Re: Problem calling a function from my vhdl project in Vivado.

    You need to think what this means:
    (9 downto ((64-conv_integer(divide))*10)

    Let start to see what happens if Divide = 64
    you get the range (9 downto 0).

    If divide > 64 on the RHS you get 10...
  13. Closed: Re: What is the future of Boolean algebra-based languages and methodologies?

    Sorry, I really meant to say that C to gates hasnt really taken over. All it really does is open up the market for Intel/Xilinx, especially now they could be losing market to GPUs. If you think about...
  14. Closed: Re: What is the future of Boolean algebra-based languages and methodologies?

    I started in VHDL and Verilog nearly 15 years ago. About 10 years ago there was a lot of talk of tools like HDL Coder from Mathworks, Handel C from celoxica making HDL coders redundant because...
  15. Closed: Re: Two questions about HDL designer - simulation and attributes

    HDL designer is just a wrapper around existing HDL. All simulations are done in HDL. So you should be able to modify a block that examines a signal anywhere in the design using external names.
  16. Closed: Re: Difference between TRN and AXI4-Stream

    Ive never used TRN, but looking at the datasheet it is similar to AXI4 Streaming. First of all, everything is active high in AXI
    dst_rdy = tready
    src_rdy = tvalid
    teof = tlast
    trem = tkeep
    td =...
  17. Closed: Re: Determine whether a binary number is of power of two in verilog code

    Yes, but it assumes but it has the following limitations:
    1. It doesnt allow for In = 0 (2^0)
    2. It is always 8 bits.
    The previous case covered the 0 case and allowed for any length of bits
  18. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    anc_line is just a pointer to a string. When you read the line the 'range will be (1 to LINE_LENGTH) where LINE_LENGTH is the length of the line in chars, not words. In your example, it means the...
  19. Replies
    3
    Views
    324

    Closed: Re: Testbench input stimulus

    Lets tackle these one at a time.
    1. Repeat. It is exactly as you expect. repeat (2) means repeat the following statement 2 times. In your case,
    repeat(2) @(posedge clock);

    means wait for 2...
  20. Closed: Re: Determine whether a binary number is of power of two in verilog code

    @barry - I was going to say that , but it doesnt work.

    1011:

    1 XOR 0 = 1 XOR 1 = 0 XOR 1 = 1

    So you dont get a power of 2.
  21. Closed: Re: Help to make use of an .h file in my vhdl code

    Yes an no.
    I suggest you learn VHDL from a tutorial.
  22. Closed: Re: Help to make use of an .h file in my vhdl code

    Of course it does, because it is Verilog code, and hasnt been compiled. So it is neither a package or in a library.
    You need to manually re-write it in VHDL yourself. a .h file is NOT a VHDL package...
  23. Closed: Re: Help to make use of an .h file in my vhdl code

    It wouldnt be included as a libarary - a library is a collection of design units. It would be included as a package, that is compiled as a design unit into a library.

    I would suggest that you...
  24. Closed: Re: 10 millisecond counter with different frequencies

    It depends if your goal is to have it change in real time, or parameterised before the build?
    Either way, you need some mechanism to work out what the counter needs to count to based on the sys_clk...
  25. Closed: Re: Help to make use of an .h file in my vhdl code

    .h (and verilog vh or svh files) files are usually included via use of a pre-processor that simply dumps the contents of the included file into the source file where they are included before the...
Results 1 to 25 of 500
Page 1 of 20 1 2 3 4