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Type: Posts; User: timof

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  1. Closed: Re: Why do we need a power splitted transistor ? (Analog layout)

    Shared diffusions are used everywhere, even in very advanced nodes (such as 7nm or 5nm), so it's not a universal rule.

    Indeed, what you say makes some sense.
    When a diffusion area is shared, the...
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    Closed: Re: How to post-sim by a PEX extracted netlist?

    If there is LVS error, usually, the parasitic extraction either cannot be run, or its output may be bogus.
    (it depends on what kind of LVS error you have. For example, if you have nets shorts - your...
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    Closed: Re: Highlight as flattened using Calibre XOR

    This is trivial to do in klayout (free, open source layout editor/viewer).

    http://klayout.de
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    Closed: Re: SRAM RC Extraction Simulation

    The problem of a large difference between post-layout circuit simulation and schematic simulation is a very common one.

    The usual process to debug this is to find out what parasitic elements are...
  5. Closed: Re: Resistor, capacitor and MOSFET corneres relationship

    You forgot to include corners for BEOL (for parasitics).

    - - - Updated - - -

    There are other factors affecting Vt - such as channel implant, gate material, etc. - that are (or may be) different...
  6. Closed: Re: DC operating output voltages of the Fully differential amplifier is not equal

    Things to check:

    1. devices are matched (all instance parameters are the same, for matched devices, for all fingers).

    2. Parasitics (parasitic resistance) - should be matched as well.

    (Doing...
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    Closed: Re: parasitic cell blocking

    I think it should be expected that performance deteriorates when you instantiate your cell at higher hierarchy, due to interconnects parasitics.

    Why do you think your parasitics in the pcell are...
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    Closed: Re: Question Regarding Max Current Per Width

    Normally, every technology provided by the foundry (and definitely - 180nm from TSMC), comes with rules for current densities for electromigration.

    These rules are described in electrical deign...
  9. Closed: Re: IC tape-out with TSMC - export license required?

    This is something that should be discussed with an export control lawyer, not at the discussion board.
    What if someone says "yes", or says "no" - would you follow that direction based on such an...
  10. Closed: Re: How to choose optimal wire width of spiral coil to attain high q factor?

    All major vendors of EM analysis tools - Integrand (EMX), Helic (VeloceRF), Lorentz (PeakView) - provide tools to synthesize an inductor layout to desired characteristics (L, Q, ...).
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    Closed: Re: Properties of MIM capacitors

    There are tons of data on MIM capacitors in the literature - check this paper, as an example, and its citations:

    J. A. Babcock et al., "Analog characteristics of metal-insulator-metal capacitors...
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    Closed: Re: Understanding LVS results (hierarchical)

    The ports on the layout are defined by text labels "attached" to port/pin text layers.

    Normally, the ports are defined at the top level only.

    There is a command in Calibre (involving "TEXT...
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    Closed: Re: Two polysilicon layers for gate connection

    If there are many metal layers in a process (let's say, 10 or 15), lower metal layers are thin and highly resistive, and upper metal layers are thick and low resistive.
    That's why top metal layers...
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    Closed: Re: Semiconductor software simulation

    https://tcad.com/Software.html
  15. Closed: Re: Temperature mobility degradation factor (c) - MOSFET SOI

    Any textbook on semiconductor physics will have something on this topic.

    Or you can look it up at Wikipedia:

    https://en.wikipedia.org/wiki/Electron_mobility

    Check the section on "Temperature...
  16. Closed: Re: Temperature mobility degradation factor (c) - MOSFET SOI

    This is an empirical equation or model, describing a temperature dependence of carrier mobility.
    Mobility decreases with temperature, that's it.
    "C" is a fitting parameter, that hsould be found...
  17. Closed: Re: Lectures or textbooks related to high-speed wireline circuits and systems?

    How about this:
    ...
  18. Closed: Re: [moved] Value of lateral electric field(E0) in UMC 65 technology

    Lateral electric field in a MOSFET is not constant, it has a sharp peak near the drain.
    But I doubt that such a deep microscopic characteristic, even if known, would be used in an empirical...
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    Closed: Re: Biasing an array of current steering DACs

    And even within one DAC, make sure that the voltage drop along the ground net, feeding the current sources, does ot create too large Vgs mismatch across current sources.
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    Closed: Re: Cannot generate calibreview pop-up after PEX

    OK, thanks.
    Indeed, some problems go away after you restart Virtuoso.
    It's probably the first thing to try, when debugging such problems.
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    Closed: Re: Cannot generate calibreview pop-up after PEX

    Why do you need a pop up window?
    If you selected Calibre View as output post-layotu netlist format, the extraction tool should just generate it. Check your directory, for the presence of this file.
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    Closed: Re: DAC unit cap selection for SAR ADC

    A high attention should be paid to wiring parasitics - which may destroy your matching / binary weighting of the capacitors in the capacitor bank.
    Use field solver (built-in in all standard...
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    Closed: Re: Polarization MOSFET SOI

    In FDSOI technologies, adaptive back bias (voltage applied to substrate or well under BOX) is a popular and common technique to control leakage vs performance tradeoff.
    Positive voltage will lower...
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    Closed: Re: Polarization MOSFET SOI

    Questions:

    1. What do you mean under "polarized" - applied voltage, or doping type? (I think, you mean the former).
    2. What do you mean under "bulk" - body of SOI MOSFET, or substrate region...
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    Closed: Re: TSMC65nm CRN65LP PDK Calibre and PEX Issues

    This post at Mentor Communities webpage may help you:

    https://communities.mentor.com/thread/10952

    This post gives some pointers to the documentation, and explains the idea and flow.

    The...
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