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  1. Closed: Re: Real time voice encryption/decryption with FPGA

    I think the question had more to do with framing the incoming data so they can tell where the AES blocks are.

    You should probably frame the AES blocks with some sort of encapsulation so you can...
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    Closed: Re: Introductory literature on PLD

    So a CPLD, which is much larger than a PLD. You'll probably want to do as wwfeldman posted and read the data sheet, but you'll probably also want to get a book or read an online tutorial on VHDL or...
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    Closed: Re: Introductory literature on PLD

    Actual PLDs? e.g. 22V10, 16L8, etc?

    or are you learning about something more modern and in current use and just referring to a programmable device as a "PLD".

    PLDs still exist but aren't used...
  4. Closed: Re: please can you explain me this font 8X8 row and col adress

    This is a mux with the lower bit of CounterX being the select which is what the text above it describes

    So for 8-pixels you need 2 clocks. I'm assuming the raster8 contains the pixels and the LCD...
  5. Closed: Re: Working with multible libraries in Modelsim

    use vsim with a -L <library> option
  6. Closed: Re: Verilog code for 8 bit register with read/write

    I figured the OP meant they wanted to connect an 8-bit register to an AXI slave interface, but doesn't understand how to do that.

    i.e. AXI master ==> AXI slave ==> 8-bit register

    A quick search...
  7. Closed: Re: $urandom for error insertion in Systemverilog

    I'm not sure what you are expecting, but the for loop is going to cycle through all 10 iterations in 0 ns.

    The entire structure of this testbench doesn't make a lot of sense to me and is more...
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    [SOLVED]Closed: Re: Comparator gives wrong Output

    Since the question wants you to compare values for greater than the inputs x and y should not be single bits but should instead be a vector, so they can be more than just 1'b1 and 1'b0.

    If they...
  9. Closed: Re: $urandom for error insertion in Systemverilog

    Can't help you if I don't see the code.
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    Closed: Re: damaged remote control

    Your first post is from 8/16 (Today) at 6:58 AM, and says you have the remote fall into a pot of tea last night.
    Subsequently a user suggests putting it in rice for a 1 or 2 days.
    And you reply I...
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    Closed: Re: verilog code using vivado

    Something tells that they are using the input pulse signal as a clock and didn't define anything for it. Based on the name alone sig_in and the names of the registers being clocked.
  12. Closed: Re: $urandom for error insertion in Systemverilog

    Only the last one because Verilog/Systemverilog loops are unrolled at compile time. They represent multiple instances of whatever is in the loop and not sequential operations.

    You also have a typo...
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    Closed: Re: Reset problem in ds pic33ep512mu810

    That's probably the line where they check the reset input but didn't debounce the signal properly, so the program calls fCrashAndBurn() instead of fGrindingSmoke.
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    Closed: Re: dspic30f2010 Used Sinewave Inverter

    You are missing the point of how this forum works.

    1) you can get help with understanding the theory of something
    2) you can get help fixing problems with your code or code you got from somewhere...
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    Closed: Re: Error in subtraction with 2's comp method

    To perform subtraction in 2's complement the subtrahend of -4 is in binary:
    100
    011 - invert
    100 - +1 (hmm result is -4)
    011 - minuend
    111 - add 2s comp subtrahend and minuend (no carry)

    The...
  16. Closed: Re: Strategy for a multi signal generator using a MAX10

    You perform verification of the design before you build a physical version of it. What you are doing is testing unverified code on hardware.

    If you were going to build an ASIC from Verilog like...
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    [SOLVED]Closed: Re: Modelsim clock signal

    I had considered pointing this out, but at least they are trying to simulate something, most posters don't even do this much simulation. Instead they immediately go to synthesis and implementation...
  18. Closed: Re: Verilog code for 8 bit register with read/write

    If you are using Vivado there is an example slave design for AXI that you can have the tools generate.

    You can also download any of the AMBA spec free after signing up on the ARM website.
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    [SOLVED]Closed: Re: Modelsim clock signal

    Don't know. I would still just type the commands in, the syntax is straight forward and easy to learn. Besides you can put them in a file and just run the from the command line without having to...
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    [SOLVED]Closed: Re: Modelsim clock signal

    Because it doesn't force a signal onto a object. I'm not even sure what that command does as the version of Modelsim I use 10.5 doesn't even have that menu item.

    You should learn the modelsim...
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    [SOLVED]Closed: Re: Modelsim clock signal

    force clk_name 0,1 5 ns -r 10 ns

    0: time 0 value
    1: value applied at 5ns
    -r or -repeat: to repeat at some interval
    10 ns the repeat interval

    this generates a 100 MHz clock you can change the...
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    Closed: Re: Error in Parity bits of Hamming Code

    First of all your statement "The very first link that you provided, calls data+parity the syndrome" is incorrect the linked text reads as follows

    That is the computed syndrome is the parity...
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    [SOLVED]Closed: Re: Failing to program ALTERA Max 7000A

    Usually it requires reading the standard, occasionally you might find a tutorial that describes the highlights of the standard. JTAG isn't that hard of a standard to understand, though I've forgotten...
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    [SOLVED]Closed: Re: Failing to program ALTERA Max 7000A

    The six 1s on TMS will force a JTAG TAP FSM to the reset state from anywhere in the TAP FSM. It's why TRST is optional.

    From power on reset a device is supposed to output it's ID when initially...
  25. Closed: Re: Strategy for a multi signal generator using a MAX10

    This is the wrong way to "fix" the wires vs regs. It will result in warnings in a language compliant simulator as reg is not the same as wire even in Systemverilog. It seems to me that Quartus is...
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