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Type: Posts; User: rangermad

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  1. Closed: Re: How to Solve the “Naming Error” in the LVS

    You have a number of discrepancies. Start with fixing your port error.
  2. Closed: Re: Why we should choose even number of finger

    How you put in the number of fingers in the schematic may effect your simulations. A transistor with a width of 1000u, mult of 1 is different then a 1000u transistor with a mult of 10 which if...
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    Closed: Re: The issue of Assura LVS

    Do you need a complete guard ring for LVS or just a nwell/pwell tie?
  4. Closed: Re: PMOS WELL of same bulk potential of different transistor groups

    Only the design engineer can give an adequate answer to your question.
  5. Closed: Re: layout connection using different metalization layers

    Check your layout design rules. Is your metal 4 considered "top metal" by your design rules?
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    Closed: Re: Hot NWELL warning in layout design

    Any NWELL you have connected like this will get flagged due to potential latch-up issues. Be sure to ring the NWELL with a PSUB contact ring. Also, try to keep these NWELLs as far away from ESD...
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    Closed: Re: No connection for Nwell

    Why have a NWELL with nothing inside of it? The assumption is that a device will be inside the nwell. So, all nwell will need to be connected to some potential.
  8. Closed: Re: DRC Error: N+SD Iso Psub tap spacing must be

    Sounds like you need to add a psub tap next to your N+SD.
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    Closed: Re: LFoundry layout design rules

    Not sure this is correct. Assuming this is a simple mos device then the connections are S/D(gate) on left or right, GATE(Drain) on top, body(Source) on bottom.
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    Closed: Re: x snap spacing and y snap spacing

    Your DRC deck should have some off grid checks. Go ahead and draw something on a 0.0000001u grid and see what happens.
  11. Closed: Re: Inter-digitization Pattern and Dummies for MOS Layout

    I would probably do AB AB AB AB with dummies on both sides. Much depends on the preferences of the design engineer
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    Closed: Re: N-well antenna effect

    The charge build up may not be from the gate to body of the mosfet. It can also be the body to gate of a mosfet. So during processing, before contact and metal, there can be a charge build up on the...
  13. Closed: Re: Difference between single flat cell check and hierarchical layout (hcell) check

    Kind of hard to help you with the limited amount of info you posted.

    A port issue can come about by cross connecting symmetrical circuits. For example, bias1 and bias2 are currents coming from...
  14. Closed: Re: Difference between single flat cell check and hierarchical layout (hcell) check

    Sounds like it could be a port issue between COMP1 and COMP2. Probably in a symmetrical circuit that connects to both COMP1 and COMP2.
  15. Closed: Re: Query regarding using layout L in cadence

    Don't know about your pin problem but the first problem you have in the lack of L and XL licenses.
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    Closed: Re: STI from all four sides

    STI totally surrounds active areas so ... yes, STI effects the gate region from all four sides.
  17. Closed: Re: Is it possible that lvs passes but ERC/Softcheck fails

    Yes. LVS/ERC are only as good as how the rules are written. In the case of a softcheck, the rules have to define all possible conductors and how they interconnect. If the a possible conductor is not...
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    Closed: Re: RF vs VDD Pad Design Techniques

    Your RF pad may be a problem. Check your design rules and make sure the pad does not require metals/vias underneath the pad metal. Also, run DRC to make sure you haven't missed anything.
  19. Closed: Re: Resistor Sizing makes Width too big for layout

    A little more info would be helpful. Can you provide a pic of your schematic and resistor options?
  20. Closed: Re: Can you suggest me how to draw layout of ISFET

    ISFET on an IC? Is this a MEMs type of device?
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    Closed: Re: rectangle at the bottom of PMOS layout

    Your top square appears to be a gate contact. The bottom rectangle looks like a body tie.
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    Closed: Re: Resistor Layout - Unit Cell Selection

    A rule of thumb would be to choose the unit size that will give you the least number of resistor segments in the area you have to work with.
  23. Closed: Re: Auto Instance Name Display in Virtuoso Layout

    IF you did a placement using XL. then turn on "Show Name Of Instance" in the Display Options GUI
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    Closed: Re: "np" layer and "pp" layer in CMOS circuit

    All of your logic gates will share one big nwell. You won't need a nwell/sub tie for every gate. The layout design rules should specify the max distance between ties. You may add them as you have...
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    Closed: Re: DRC metal density issue. How to fix it?

    Metal density errors can be ignored until you run your top level cell.
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