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  1. Closed: Re: Comparator characterization for variable input

    http://ww1.microchip.com/downloads/en/devicedoc/31003a.pdf


    The MOSFETs of the technology i'm using having a reset as a digital input means that the smallest W/L are used

    The threshold voltage...
  2. Closed: Re: Comparator characterization for variable input

    I don't have a specific MC i have looked some datasheets but couldn't find information about the capacitance i just used a 100fF C as a guess for the capcitance of the MOSFET, i also have to consider...
  3. Closed: Comparator characterization for variable input

    Hi, I'm using a single stage amplifier IC design as a comparator for generating a reset signal when the input voltage goes below the refrence voltage (0.7V), the input voltage is produced by a...
  4. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    well thanks for your answer i could achieve it with only 2 flipflops with the reset pulse connected to the reset pin and it just does the required. Thanks for your effort though


    yea actually the...
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    Closed: Re: pulse width stretching

    oh that'S much more simple than i was thinking to do! thanks a lot
  6. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    Yea that was my question if i can achieve that with some flipflops as it's an ic design so i can't use a ready ic
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    Closed: Re: pulse width stretching

    I tried generating a set signal from the rising edge of the pulse i got and feeding it as a set signal for the "counter" which is a d-flipflop with its D connected to the Qn. The problem right now is...
  8. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    I'm trying to do both variants, so i thought delaying it digitally would be easier.



    I tried generating a set signal from the rising edge of the pulse i got and feeding it as a set signal for...
  9. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    i have a 50MHz clock provided so i was thinking about delaying it digitally without using any capacitors as another solution for at least 2 cycles (40ns) by using a Dflipflop as a frequency divider...
  10. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    implementing a counter would be complicated especially that i need to delay it for only 2 clock cycles and i guess the counter would stretch both pulses?
  11. Closed: Re: Adding a pulsed switch to a dc voltage source in cadence library

    I have simulated the switch with the following parameters but it's still giving the input signal

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    Closed: Re: pulse width stretching

    ok one last question, is there a way to stretch it digitally for around 100ns only without having to use the RC?
  13. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    ok is there any possible way to stretch it for around 100ns digitally without using the RC?
  14. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    the RC could be added outside or i can just reduce the time
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    Closed: Re: pulse width stretching

    I'm sorry if i have overlooked your post and generally for being not well informed about the topic. My apology to all of you guys.
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    Closed: Re: pulse width stretching

    That will still be possible by connecting the RC outside the chip

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    if you could tell me what is a schmitt AND gate it would be great so that i can implement it. Is it just an...
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    Closed: Re: pulse width stretching

    yes, sorry i should have mentioned it in my original post but i have already mentioned it in my answers
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    Closed: Re: pulse width stretching

    no i need to simulate it in cadence as it's a part of another circuit. i have googled it but didn't find anything related
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    Closed: Re: pulse width stretching

    It is but it's not directly realizable so i wanted to know does it consist of
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    Closed: Re: pulse width stretching

    I'm using Cadence so i have to implement it whether as digital gates or transistor level
  21. Closed: Re: stretching the 0 pulse of a digital output with a certain T

    Timing is about 50-100ms. Supply voltage 3.3V and it's an integrated circuit
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    Closed: Re: pulse width stretching

    Realizing this schmitt trigger with 2 inputs
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    Closed: Re: pulse width stretching

    i got your point and i want to simulate your approach that's why i'm asking how to realize the circuit you drawn itself
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    Closed: Re: pulse width stretching

    ok i still didn't get the design you meant. Is it an AND Gate with the RC connected to one input?
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    Closed: Re: pulse width stretching

    the duty cycle is varying it could be anything as this is a trigger for a reset signal. and the stretch time is ca 50-100ms as mentioned
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