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  1. Replies
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    Closed: Re: Pulse power dissipation in a BJT

    It's hard to find thermal time constant data for discrete
    devices (let alone ICs).

    Now when you say that space is constrained, does that
    mean you have no plan for a heat sink? What is thetaJA...
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    172

    Closed: Re: Wrong output in HSpice

    Maybe the problem is "another lab" and not the software
    version. Inspect the log file for warnings about missing
    .LIB target. Inspect the target model files to be sure they
    are where and what you...
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    Closed: Re: Voltage drop using 1 MOS

    Using a MOSFET as a "diode drop" is a pretty poor idea
    if you want any decent tolerance. Too much variability.
    At very low current you would need a very long and
    narrow device to get that much...
  4. Closed: Re: Off-the shelf transformer for push pull converter

    I'm pretty sure I've seen Coilcraft transformers that
    they say are for push-pull.

    One issue with push-pull is the potential for "flux
    walk", accumulated duty cycle imbalance on the
    A/B phases...
  5. Closed: Re: Resistance of component bag made of "reddish" ESD plastic?

    There exist ESD-safe work totes / tubs for carrying WIP
    around from station to station. You'd only need a couple,
    maybe a cart with drag-chains to keep at "floor potential",
    and the discipline to...
  6. Closed: Re: How to parallel process foreach_in_collection in ICC?

    Consider breaking it up at least by major-loop iterations
    and farm it out to N processes each with a slightly
    differentiated circuit file. Then you just have to combine
    the data.

    If you're...
  7. Closed: Re: Resistance of component bag made of "reddish" ESD plastic?

    Somebody needs to do the cost / benefit analysis of
    proper ESD protection (floor, surface, ionizers, RH
    control) vs the labor and material costs of blowing sh!t
    up over and over and then chasing...
  8. Closed: Re: Where to get schematics about SCRs full-wave triggering circuits ?

    Old SCR databooks sometimes had a lot of application circuits.

    Here's a list of RCA app notes they called out back in 1978.

    I'd bet that "application note scr trigger" would turn up a
    hit or...
  9. Closed: Re: Sampling Bandwidth vs. Bandwidth in Tracking Mode of a Sample/Track and Hold

    Depends how you like to define bandwidth.

    Small signal bandwidth as -3dB from flat-top, is not
    a very useful descriptor of a T/H amp's performance
    when what you care about is a settled-to-N-bits...
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    Closed: Re: bipolar active linear region

    The definition is arbitrary and does not comprehend
    that the "saturation region" is a continuum of declining
    hFE and Rc, both, as Vce approaches zero.

    Check out the relation of "forced beta"...
  11. Closed: Re: [LAYOUT] When pcell is created created, bulk and gate are shorted!

    I do not see the gate contacts. Maybe there is a field / box
    pertaining to how they should project from the body, which
    would then push out the "B" ring.

    But the possibility of a defective...
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    [SOLVED]Closed: Re: Delay time calculation

    Perhaps there is a built-in clock prescaler (like, to make
    a 4-phase field from a 50MHz main clock)?
  13. Closed: Re: Noise coupling into DCDC module via the ground copper pour directly beneath it?

    I would expect that the DC-DC inductor is the EMI aggressor,
    but DC-DCs also contain "victim" circuitry which means they
    can "self-harm" very easily (charge pumping Vref or FB pins,
    FET...
  14. Closed: Re: kick-back on the diode voltage current mirror

    You would prefer to "steer" current softly, rather than
    hard-switch it. Switches have charge injection and a
    scheme that connects, disconnects abruptly can make
    charge "find its own way out".
    ...
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    Closed: Re: Integration methods when simulating

    Maybe not "normal" but not unheard of. You can run into
    numerical issues in high gain circuits, varying by integration
    method.

    TRAP has the problem of being underdamped / undamped.
    If you...
  16. Closed: Re: How to extract vt and gm max from SPICE

    Do you know how to measure these using lab equipment
    on physical samples?

    Do you have a testbench schematic or netlist which has
    implemented these tests' stimuli and loads electrically,
    and...
  17. Closed: Re: Transient testing rig for 3720W power supply with DCDC modules.

    It seems over-elaborate for what is basically a bank
    of resistor-to-ground shunts.

    There's an outfit selling "load slammer" products
    for this role. I made my own about a decade ago.
    Not as...
  18. Closed: Re: Extending the NPLUS layer between two PMOS transistors

    Some technologies make PPLUS = !NPLUS (or vice
    versa) saving them one mask level's reticle cost and
    eliminating the creation of a field implant mask as
    another step / cost-point.
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    Closed: Re: MOSFET capacitance estimation

    I don't think you can do it very well. "Size" is a "bin" of
    rough die area, but this is loosely coupled to gate area
    and technology type (hex, trench, superjunction) will
    all have very different...
  20. Closed: Re: Extending the NPLUS layer between two PMOS transistors

    NPLUS and PPLUS are hard-masked by ACTIVE so simply
    putting (say) PPLUS somewhere doesn't mean PPLUS is
    present on the silicon.

    Spacing rules for the "soft mask" of NPLUS. PPLUS may be
    too...
  21. Closed: Re: Max Overdrive Supply Voltage in SoC 5nmFinFet

    I would not take anyone's opinion besides the foundry's
    reliability documentation (you want it in writing, yes, you
    do). Especially since you seem to want a specific life
    expectancy, only the...
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    Closed: Re: Setting Ron or Rds of LDO

    You probably want a substantially lower Rout, else as you
    approach the dropout voltage you will "wind up" the error
    amplifier and have no authority (small signal) over the
    output.

    The Vgs you...
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    Closed: Re: PDK tt_pre vs tt_post

    _pre would contain the intra-FET metal-poly (as part of cgdo,
    cgso) and the EM simulation will also grab that onto the nets
    involved. So double counted. I'd use the _post any time you
    are doing...
  24. Closed: Re: Non Overlapping Clock Generator(4 outputs with same frequencies as the input cloc

    If all you want is "enough" switch throw time nonoverlap
    then you could do it with combo logic and delay stages.
    Tuning it up to match will be an exercise and from there
    PVT "is what it is".
  25. Replies
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    391

    Closed: Re: PDK tt_pre vs tt_post

    For one thing, parasitic extraction will pick up the poly-
    metal, metal-silicon capacitances of the core FET which
    are already built into the _pre model. This would be an
    added penalty on the...
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