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Type: Posts; User: shaiko

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  1. Closed: Avalon MM - using a FIFO with a registered output

    Hello,

    I have an Avalon MM interface of which I'm the master.
    The data that I want to write to the slave is buffered in a FIFO.
    To achieve better timing - I want to use a FIFO with a registered...
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    Closed: Re: OpenCL vs VHDL running in FPGA

    Regarding your question.
    Comparing VHDL and OpenCL as 2 languages is misleading.
    OpenCL is MUCH more then just a "Higher Level" language. It's a complete framework that describes communication...
  3. Closed: Re: How is data transferred from memory to PCIe cards?

    So if we examine the TLP layer messages running over the PCIe link - we'll usually see the NIC's hardware asking for data from the South Bridge and the South Bridge responding to it ?
    As opposed to...
  4. Closed: How is data transferred from memory to PCIe cards?

    My question is about data transfer between a PCIe peripherial and system memory. Example: Suppose we need to send a big chunk of data ( stored in system memory ) over an Ethernet network.

    How will...
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    Closed: Re: Link Training with IO DELAY

    At 100MHz - why do you want to use a SERDES ?
    Why not implement a simple synchronous interface (like SPI) ?
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    Closed: Re: Link Training with IO DELAY

    What is your communication protocol ?
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    Closed: Re: Link Training with IO DELAY

    Yes.
    The "bitslice" is an IOSERDES, IODELAY and FIFO aggregated into one primitive.
    Before Ultrascale - series 7 had these separately.

    The new approach is what Xilinx calls: "Native Mode".
    The...
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    Closed: Re: Link Training with IO DELAY

    In essence - "link training" is the process of finding the safest sampling point at receiver to avoid timings violations and achieve a robust link.
    In the Ultrascale family the recommendation is to...
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    Closed: Re: Parent signal when alias is accessed

    So it should fail during p&r ?
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    Closed: Re: Parent signal when alias is accessed

    If it was then driving x<='0' would also reset y (18) ??
    Why would anyone write such code?? It "hides" logic and hurts the readability...
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    Closed: Re: Parent signal when alias is accessed

    And what if Y was driven by another process of the same architecture ?
    Will this be legal ?
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    Closed: Parent signal when alias is accessed

    Hello,

    While debugging an old design I came across the following code:


    alias x : std_logic is y ( 18 ) ; -- y is a 32 bit wide std_logic_vector input port.

    begin

    process ( clock ) is
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    Closed: Unfamiliar VHDL | operator

    Hello,

    What does the VHDL '|' (like bitwise or in C) operator do ?
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    Closed: Re: VHDL unconstrained array in VCS

    Yes. Waiting to hear back...
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    Closed: VHDL unconstrained array in VCS

    Hello,

    In my design I use arrays of unsigned vectors. For this purpose, I define an unconstrained array type inside a package as follows:

    type generic_array_unsigned_1d is array ( natural range...
  16. Closed: Re: System Verilog - default type of a declared variable

    What do you do in your designs?
    Suppose, a signal is indeed logically a wire - do you explicitly declare it as a such?
  17. Closed: Using different time units in Verilog simulation

    Hello,

    In VHDL one can use different time units to schedule simulation events. For example:

    x <= '0' , '1' after 2 ns , '0' after 4 ms ;

    From what I know for similar purposes Verilog uses...
  18. Closed: Re: System Verilog - default type of a declared variable

    But isn't writing`default_nettype none equivalent to not writing anything at all ?
  19. Closed: Re: System Verilog - default type of a declared variable

    With SV, is there a good reason why not declare all variables and ports as type "logic" ?
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    Closed: Parameter location in a Verilog Module

    Hello,


    I noticed that in Verilog both of the constracts below compile correctly.
    // some_parameter is used after some_input
    module some_module
    #(
    parameter some_parameter
    )
    (
  21. Closed: System Verilog - default type of a declared variable

    Hello,

    As far as I know (correct me if I'm wrong), if we declare a variable in Verilog without explicitly giving it a type - it defaults to a "wire".
    Is this rule the same with System Verilog ?...
  22. Closed: Verilog & System Verilog - port sizing by inheritance

    Hello,

    VHDL supports leaving the size of component ports unconstrained during declaration.
    Unconstrained ports are constrained during elaboration by inheriting the sizes of the signals we connect...
  23. Closed: Re: Passing a pointer to an array as argument to function

    And suppose I want to pass the function a pointer to a 3 element array (not only to the first one).
    What will be the syntax for that ?
  24. Closed: Re: Passing a pointer to an array as argument to function

    If I want to declare a pointer to an array of 3 elements in my code I use:

    float (*pointer_to_array)[3]

    But you pointed out that if I want to pass a pointer to a function - I should write:
    ...
  25. Closed: Re: Passing a pointer to an array as argument to function

    So what will be the difference between these 2 examples:


    func(float * arg)


    func(float * arg[3])

    ?
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