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  1. Replies
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    Closed: post lna contribution to system noise

    of course it is correct
  2. Closed: Re: [20 pts] [urgent ] Boolean equation simplification

    c+ab
  3. Closed: Re: how to match 2.7 mH+100ohm reactance to 8 ohms?

    0.5 ohms of resistance is included to model the wire resistance of the 7 windings.
  4. Closed: Re: how to match 2.7 mH+100ohm reactance to 8 ohms?

    yes there is!

    using the 2.7mH as an autotransformer in boosting fashion, and a 1.4nF capacitor.

    i asked this question to see if anybody is aware of this trick, and my head is still not very...
  5. Closed: Re: how to match 2.7 mH+100ohm reactance to 8 ohms?

    what is the wisest way of matching 2.7mH+100ohm reactance to 8ohms?
    at 80kHZ?

    thanks.

    Added after 9 minutes:

    ofcourse, without using inductors in the milli henries range.
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    Closed: Re: Which one is more important? S11 or S22?

    depends on the stage of the system you are designing. I wouldnt care too much about s11 if that is my first stage amplifier.

    Added after 2 minutes:

    yeah but the first stages are better if...
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    Closed: rectangular coil E field

    how would i calculate the E field induced in the plane parallel to the rectangular coil within which timevarying current flows?

    please help.
  8. Closed: neuronal gating equation (multiplication) in spice?

    hi.

    i want to model the following equation in spice:

    dm/dt + (alfa(v)+beta(v))*m = alfa(v)

    where alfa and beta are dependent variables on 'v'.
    but evidently this requires multiplication.
    ...
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    Closed: design at high frequencies?

    at high frequencies TLs start to radiate. so, what design considerations should be applied at high frequencies?
  10. Closed: Re: sram design

    because sometimes speed matters. you need a relatively high capacitance at the end of the mos transistor to store the bit, and that slows down the read-write operation.

    ".. Ccell must be...
  11. Closed: Re: 8-bit adder

    among tree adders, kogge-stone is the fastest since it requires fewest number of series logic levels (4 levels for 16bit addition actually); however, that requires a good deal of hardware (in...
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    Closed: Re: why does a mos transistor saturate?

    hey, thank you for that!
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    Closed: Re: why does a mos transistor saturate?

    what happens to Vp @ Vds>Vgs-Vt ?? doesnt Vp increase as we keep increasing Vds?

    if it does increase, how do you explain the constant current.
    if it does not incrase, why?

    thanks.
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    Closed: Re: why does a mos transistor saturate?

    nice!

    however.. why the pinch off point has a constant voltage Vp?? What is Vp?
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    Closed: Re: why does a mos transistor saturate?

    Ids remains (nearly) the same, even though the drain voltage is increasing with respect to source. Why? What is the underlying physics?

    thanks in advance

    Added after 18 minutes:

    i need a...
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    Closed: Re: while loop depending on input argument

    can show me a source stating that while loops are not synthesiable?

    indeed, if while loops were not synthesiable my synthesis tool would generate an error message stating that "it is not...
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    Closed: while loop depending on input argument

    (cross posting)

    now this is a very basic question:

    The code seen below goes to infinite loop during synthesis, hence my sythesis tool halts (with an error like, "loop has iterated 64 times so...
  18. Closed: while loop depending on an input argument

    now this is a very basic question:

    The code seen below goes to infinite loop during synthesis, hence my sythesis tool halts (with an error like, "loop has iterated 64 times so i am halting blah...
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    Closed: adc placement setting

    hi,
    sorry guys, this is an ameturish (and a bit long) question. however i need help:

    i have to design an array of DACs (operating around 50KHz) which will drive an array of large capacitors.
    ...
  20. Closed: Re: is there a limitation to paralleling MOS current sources

    thanks for replying.

    actually i am going to design a DAC. since monotonicity is important for me i decided to include as little resistors as possible (maybe non), and that implies big arrays of...
  21. Closed: is there a limitation to paralleling MOS current sources?

    hi,
    in my design, i figured out that i need a large array of current sources (maybe a thousand of them or more). is there any limitation, drawback of paralleling so many current sources?

    thanks...
  22. Closed: Re: two port device with a linear i-v characteristics

    thanks for your reply, but is it possible to get rid of that offset value you have mentioned?
  23. Closed: c-2c ladder

    thanks for answering but i have 2 objections:

    1) i am quoting from "electronic analog-to-digital converters" by Seitzer and Pretzl:

    "..in view of the progress of MOS technology with its...
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    Closed: Architecture for 10 µm width DAC

    hi,
    which architecture should be used if we are to build a digital to analog converter (DAC) with a width not more than 10µm. what are the restrictions, pitfalls for such a design? (by the way, the...
  25. Closed: two port device with a linear i-v characteristics

    hi,
    is it possible to build a two port circuit with highly linear i-v chararacteristics? actually we call them resistors in everyday life, but i want this circuit to be consisting of only MOS...
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