Search:

Type: Posts; User: quyleanh

Page 1 of 3 1 2 3

Search: Search took 0.02 seconds.

  1. Replies
    6
    Views
    534

    Closed: Re: Deep nwell connection

    In my opinion, it is better if you use 3 dnwell separately. To prevent noise from each pwell to others.
  2. Closed: Re: Why we should choose even number of finger

    Thank you for your reply.
    But my question is comparison between 1000 and 1001 number of finger in schematic viewpoint. I mean the main ppint is odd and even number of finger.
  3. Closed: Re: Best books for Current mirrors and differential amplifiers using MOSFFET

    I can not tell you what is the best book, but let me tell you something which I think it's the best for you in this case.

    If I was you,

    I will firstly clarify which problem do I have. What kind...
  4. Closed: Re: Why we should choose even number of finger

    Thank you. It's just an exception but still intresting for considering.
    If you have any other point of view. Please let me know.
  5. Closed: Re: Why we should choose even number of finger

    My mistake, even number of finger. Does it make more convinent for you to discuss?



    Thank you for your replying. As I said, I know what is benefit from layout view point. Could you give some...
  6. Closed: Why we should choose even number of finger

    Recently I have question about why we should choose even number of finger.
    As far as I know, the even finger is easier to layout in Current Mirror, Differential Pair when we need matching. (Because...
  7. Replies
    2
    Views
    396

    Closed: Re: Layout of Serial MOSFET

    Thank you. After trying some patterns of my layout, I think the horizontal one is a bit better, although the wiring is complex.
    But as you said, it depends on actual design. The vertical pattern is...
  8. Replies
    4
    Views
    904

    Closed: Re: Common centroid matching array

    The second is seems better for matching when it has better common centroid.
    One more thing is the number finger of A and B in the second configuration should be even for abut.
  9. Replies
    4
    Views
    904

    Closed: Re: Common centroid matching array

    In my opinion, the second placement is good enough. It's simple for wiring and still get matching for A, B transitor.
    There will be trade off when we choose too complex placement. Like wiring...
  10. Replies
    2
    Views
    396

    Closed: Layout of Serial MOSFET

    In order to increase length of MOSFET, the schematic designer can connect multiple MOSFET as serial.

    I would like to ask about this configuration in layout. Should I place MOSFET in vertical or...
  11. Closed: How to find formula of calculating resistance in Pcell?

    I would like to ask how to find the formula of calculating resistance in Pcell?
    For example, whenever I change the length, the resistance is automatically updated. How can I find it?
    Thank you.
  12. Closed: Re: What is DIVA in Cadence Diva verification tool mean?

    Thank you for sharing.

    I know. But it has some cons. For example when my big layout is mess up with connection, the highlight net will mark incorrect. When I just want the Metal and Via layer...
  13. Closed: What is DIVA in Cadence Diva verification tool mean?

    Just curious, I have Calibre tool for check almost everything of physical verification. But I still need more extraction check from diva tool.

    For the one who does not know.
    We can extract a...
  14. Replies
    5
    Views
    831

    Closed: Re: Question of guard ring when layout

    Because the purpose of guard ring is separating all rfmos to other devices in circuit.
    As long as you separate all rfmos (before or after), the protection purpose is satisfied.
  15. Replies
    5
    Views
    831

    Closed: Re: Question of guard ring when layout

    In my opinion, it is safe to not add all guard ring in rfmos in the begining.

    Let's consider about the priority of your layout requirement. If it put area higher than precise of guard ring...
  16. Replies
    18
    Views
    1,434

    Closed: Re: x snap spacing and y snap spacing

    I have access to silterra130nm but I have not worked in this process, only silterra180nm for now.
    You can have some basic and readable information in this file, please check in advanced
    ...
  17. Replies
    18
    Views
    1,434

    Closed: Re: x snap spacing and y snap spacing

    But I do have to care about grid, right? Because my layout is check with DRC desk and fabricated, I have to follow the rule from manufacturer, right?

    - - - Updated - - -



    I have checked in...
  18. Replies
    18
    Views
    1,434

    Closed: Re: x snap spacing and y snap spacing

    Really??? Can I use grid 0.0000001u?
    If you not sure, don't tell so assured like that.


    For your question, you can found it in PDK document called PhysicalDesignRule.
    It's specified in General...
  19. Closed: Re: Source code of skill function of Cadence Virtuoso

    After some researches, all source skill code of cadence is pre-compile to context file (cxt) in install_dir/lnx86/tools/dfII/etc/context
    There is no way to read and de-compile. We just only call it...
  20. Closed: Re: Source code of skill function of Cadence Virtuoso

    Thank you. I know the prefix of function and operator but I just cannot find where their definition.

    I have search in cadence home directory but there is no result. May be some functions are used...
  21. Closed: Source code of skill function of Cadence Virtuoso

    I want to assign bindkey for a toolbar button. For example, Key 4 for toggle between Transparent group ON/OFF.
    In the Toolbar Manager window (when I click customize option), the callback function of...
  22. Closed: What is ref layer (stream number : datatype 0:0) in mosaic instance

    In the layout which has mosaic instance, there are layer call "ref" which is defined as 0:0 stream number and datatype. It is in tsmc technology.
    Could you please let me know which exactly it is?
    ...
  23. Replies
    3
    Views
    412

    Closed: Re: Exclusion Layers for Dummy Metal Fill

    Update: there are no DRC rule check for VIA density --> I was wrong.
    There are actually VIA density rule check for via stack. And from 40nm technology, we also have dummy fill for via.
  24. Replies
    3
    Views
    412

    Closed: Re: Exclusion Layers for Dummy Metal Fill

    As I know, there are no DRC rule check for VIA density, right?
    And technically, if your working process has required fill BOTH metal and via, and in order to protect the sensitive circuits, you have...
  25. Closed: Re: Inter-digitization Pattern and Dummies for MOS Layout

    Yes. You should add B on both sides.
    If between each groupd has space, the dummies have the same space as well.
Results 1 to 25 of 58
Page 1 of 3 1 2 3