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Type: Posts; User: dick_freebird

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  1. Closed: Re: Remove glitches in output frequency of ring oscillator

    Color-on-black is the Cadence default and simple screen
    shot is what you see. When I do "paper" documentation
    I always turn them to black-on-white, but that's another
    4 clicks per pic.
  2. Closed: Re: Remove glitches in output frequency of ring oscillator

    Those aren't "glitches". They are full scale, fully settled reswitch
    (chatter). Moreover it appears repetitive.

    Your RO should have one and only one cycle of a standing wave.
    Stop the cycle and...
  3. Closed: Re: LLC converter vs Dual cascaded Buck….1000V to 48V at 500W output…no isolation ne

    To the point of no 1kV models, the next page I hit
    on my way out from edaboard showed me this:

    https://www.eeworldonline.com/e-commerce-site-offers-designers-device-models-on-demand/
    ...
  4. Closed: Re: LLC converter vs Dual cascaded Buck….1000V to 48V at 500W output…no isolation ne

    Have you considered the "solid state transformer" as
    Stage 1? That being a fixed-duty buck with no control
    loop at all? These can be made pretty efficient and
    no compound-converter-stability...
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    Closed: Re: SMPS for 5000W can be a Full Bridge

    Ridley is still very active and putting out new material.

    He has a Facebook power supply design group that you
    could join (I think - sort of a velvet-rope deal for many
    "interest" groups, so...
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    Closed: Re: BJT amplifier design

    51dB (voltage) gain is A=355
    A=gm*Rout
    assume best case Rout=Rload
    Then gm must be 355/50K or 7mA/V

    If you can find a transistor with this kind of gm and decent Early voltage then a single CE...
  7. Closed: Re: About can't find PDK in layout in Cadence

    PDKs pertain to physical implementation at a foundry (and
    the precursor steps of design capture / synthesis / analysis).

    vcvs is an ideal component with no physical implementation.
    It is ignored...
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    Closed: Re: Fast static CMOS comparator circuit

    Static CMOS comparators are not really good when it
    comes to Vio (t=0, and drift). That's why so many are
    clocked (that, and low quiescent power).

    If you were clever and had the die area and a...
  9. [SOLVED]Closed: Re: Trouble with frying 74LS11N AND Gate

    I'd start with simple testing of those "bad" logic ICs
    and see whether the inputs all show same IIH, IIL or
    some are "out of family" and thus suspect for damage.
    Given that you seem to be...
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    [SOLVED]Closed: Re: 12V power source without any IC.

    I'm (barely) curious why you "need" to use inferior
    technology. If I had to guess, I'd guess this is a school
    project and somebody else gets to set the boundaries
    and criticize the BOM.

    Your...
  11. Closed: Re: Design Resource For Wireless Power Transfer

    I'd start with everything you can get off of ChargEdge's (sp?)
    YouTube and related technical material. Evidently there
    are a lot of bad ideas out there, including most of the big
    names, when it...
  12. Closed: Re: Understanding LVS results (hierarchical)

    There's ports all the way down, and hierarchical means
    you are checking at levels below the top so you will see
    the ports of lower level blocks checked as the local
    network equivalence checks...
  13. Closed: Re: Does It Make Sense to Connect SMD Fuses In Parallel Instead of Using Bigger One

    Fuses -need- to get hot, to work.

    You cannot depend on current matching, and a set of
    (say) 1A fuses might fall like dominoes at 1A, 1A, 1A
    rather than 3A if there's significant...
  14. Closed: Re: Smaller die size by tighter SPICE corners?

    Not so much a thing for digital, but a big deal for analog.
    Consider a case where (say) you have an "edgy" process
    flirting with impact ionization at shorter L. Your modeling
    folks might manage to...
  15. Closed: Re: Why lib file only include FF,TT and SS

    FS and SF corners are often not "realistic" (not even as
    realistic as the sandbagged SS corner). You cannot, for
    example, get a max-spec Tox on the N and a min-spec
    Tox on the P channel devices....
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    Closed: Re: Realistic Monte Carlo setup

    Foundries and their PDKs are not to be trusted.

    If you want to discover how you're being led, try a
    simple simulation of key PCM devices that are used for
    WAT. Turn on process and mismatch,...
  17. Closed: Re: Short channel effects on Transconductance(gm).

    gm is the slope d(Id)/d(Vgs). Look at the basic ID-VG
    curve and you can see that there's a slope that's
    maximum and consistent, in the subthreshold region
    (thus maximizing gm) and it rolls over...
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    Closed: Re: Peak Power Vs Rated Power

    Cheesy low end consumer audio products, back when I
    last looked, often appeared to play games with power
    ratings. Like, yeah, you can get rated power for long
    enough to run the test, but the...
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    Closed: Re: DAC unit cap selection for SAR ADC

    Besides thermal noise you care about charge injection
    from the switches, that probably dwarfs thermal noise.
    Thermal noise formula would be a minimum starting point,
    what you find for Qsw and its...
  20. Closed: Re: Is this the reason there's so few 2 Transistor Fwd Sync Rect controllers?

    It seems to me that in olden times, the datasheets were
    also where companies would put applications information
    (National especially was good in that respect). But now
    I think they prefer to...
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    Closed: Re: Phase locked Loop Locking

    To me it looks like the loop is unstable, but you really
    do need a longer run time to be sure.

    I recommend checking the VCO tune range first, it
    looks like the vctrl needs to be nearly railed...
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    Closed: Re: BSIM4 MOSFETs models

    Wouldn't you really want to pick up a SPICE package with
    BSIM4 support "baked in"?

    If not then you have to drill into the docs for whatever
    SPICE (-type) simulator you do have, and learn how to...
  23. Closed: Re: when neg. edge flop followed by pose. edge flop both have different clock then lo

    Positive, negative edge have nothing to do with it.
    The problem is non-determinstic, non-stable phase
    relation between clocks.

    A negative edge FF followed by a positive edge FF
    will do the...
  24. Closed: Re: Seeing a crisp rectangular wave on an oscilloscope

    There's probe bandwidth and there's channel bandwidth.
    Probe BW is lower as far as I've seen (because what's
    the use of more BW than the 'scope front end can pass?).

    500pS risetime is (if you...
  25. Closed: Re: Motor dummy load resistor calculator

    While not necessarily related, or closely, I have observed
    that resistor loads do not act the same "as the driver sees
    it", as windings.

    I once undertook to defeat the traction control...
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