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Type: Posts; User: TrickyDicky

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  1. Closed: Re: parameterized insertion of bits to data

    I suggest you continue on this route as this is how the majority of hardware implementations work for this kind of job.
    Have you got a circuit diagram yet?
  2. [SOLVED]Closed: Re: Need help creating Vivado Timing Constraint

    The best way to get this is to mess about in the TCL conside. start from the get_nets command and ensure it returns a list of nets you expect. Then work backwards.
  3. [SOLVED]Closed: Re: Need help creating Vivado Timing Constraint

    The "simple" option is to make the clock groups async. This has the effect of making any connections between the two clocks as false paths. But false paths are no longer prefered for CDCs. Ideally,...
  4. [SOLVED]Closed: Re: Suppressing the spacing in $fwrite command of Verilog

    Try %0d
    Look up any C or Verilog formatting on the web.
  5. Closed: Re: How do i read or write to ram address given in datasheet? using verilog

    Far far too vague.
    You need some code to control whatever the interface to provide the address and data.
  6. Closed: Re: FYP ideas suggestion on FPGA, or FPGA based network processing/network on chip

    Someone kind-of did that already:
    https://gkoberger.github.io/stacksort/
  7. Closed: Re: [moved] VHDL of input capture and output compare

    There are many VHDL tutorials on the web.
  8. Closed: Re: [moved] VHDL of input capture and output compare

    Theres your answer - it is homework. So you should be researching how to write VHDL, not expecting someone to do it for you.
  9. [SOLVED]Closed: Re: VHDL scope vs visibility vs visibility by selection

    VHDL is a procedural language like any other, with scope the same as any other language. Statements are executed in the order they are written. So during the elaboration, everything is elaborated in...
  10. [SOLVED]Closed: Re: VHDL scope vs visibility vs visibility by selection

    With VHDL 2008, you can use external names. But you can only see inside something thats already in scope. So in your example, you cannot see inside "b_block" from "a_block" because it is declared...
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    Closed: Re: Inferred VHDL dual port RAM template

    You have to be a little careful with the code, as if it goes too far from the template, inferrence may not work.
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    Closed: Re: ERROR:HDLParsers:709

    VHDL has no knowledge of Verilog. Hence directly accessing a Verilog module from a vhdl library is illegal because it doesnt exist.
    You need to use a component to give the VHDL compiler knowledge of...
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    Closed: Re: pcie hard ip altera- latency problem

    I would say there is a problem with your state machine - why cant it cope with a large latency?
  14. [SOLVED]Closed: Re: VHDL: reading text file stops at endfile()

    You have the file open procedure outside of a process. It is hitting the while loop before the file is open.

    Either open the file at the declaration or move the open procedure inside the process...
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    Closed: Re: Inferred VHDL dual port RAM template

    For xilinx you can do this by making the ram storage a shared variable rather than signal. But this never used to work for write before read in altera. Your only choice was to instantiate an...
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    Closed: Re: SystemVerilog Input generation

    This is a pretty worthless activity. Why do you need to? Is this a data bus carrying packets? You need to look into constrained random testing.
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    Closed: Re: Lattice FPGAs and Diamond software

    My main point of comparison was an RapioIO core I had to interface to in both an Altera and Xilinx device with the same code.
    Altera showed nice clean diagrams with all of the packet headers listed...
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    Closed: Re: Lattice FPGAs and Diamond software

    Since Intel bought altera, they are heading for the server market and focusing only on high-end, moving towards having CPU and FPGA on the same die so they can get high throughput between CPU and...
  19. Closed: Re: SystemVerilog Assertions into ModelSim

    SVA is usually an additional licence feature you need to pay for.
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    [SOLVED]Closed: Re: How to write in the log file

    $fflush should push any internal buffers to a file. You should be able to keep a file open as it updates (I normally do with notepad++). I am a VHDL user though (its been a while since I did SV).
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    Closed: Re: How to instantiate a submodule in Verilog

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51007.pdf
    Page 13-13
  22. Closed: Re: Timing and routing to large number of memory banks

    Getting signals into and out of rams has a timing penalty. If you have large inter-dependent rams the sources of these signals may be a long way from the ram that requires it. You may need extra and...
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    Closed: Re: Advanced VHDL book recommendation

    I would never count 1 process as "dangerous". Just needs a bit more thought if you want outputs based on current state - namely - another process/inline code that creates an output based on the...
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    Closed: Re: Advanced VHDL book recommendation

    Well that makes more sense. Ive always understood that old synthesisors (in the 90s) couldnt deal with combinatorial and sync logic in the same process, hence the need for two processes for...
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    Closed: Re: Advanced VHDL book recommendation

    I get to page three, and see this:



    use ieee.std_logic_arith.all;


    Then section 5.7 and see this:
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