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Type: Posts; User: tanish

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  1. Closed: Extracting MOSRA LEVEL 3 Parameters and values

    Do anyone know how can I extract MOSRA Level 3 parameters for a specific library file when I'm using hspice? I wanna measure the aging for standard cells of that library.
    Also do these parameters...
  2. Closed: Connecting FPGA to computer using ft232rl module

    Hello,
    I'm trying to send and receive data to/from fpga using ft232rl module(rs232). I'm using mojo v3(spartan 6 lx9). however I have tried to produce baud rate and receiver module, I'm not able to...
  3. Closed: Re: instantiate a distributed ram using core generator in xilinx ISE

    yes I know but I will use the combine of this bits in my code!
    for this reason I want to know is there any solution to reduce this long transition?it's so important for me.

    - - - Updated - - -
    ...
  4. Closed: Re: instantiate a distributed ram using core generator in xilinx ISE

    could you please explain more about DMEMs/registers?
    I defined data_out as an output port and I didn't specify that it's a reg or wire.I think in this case verilog HDL consider it as a wire by...
  5. Closed: Re: instantiate a distributed ram using core generator in xilinx ISE

    I did the xst synthesize and the maximum frequency was about 350 MHz.
    but when I do post place and route simulation there is some problem with my results.
    this is my code:


    module
    ram_top(...
  6. Closed: Re: instantiate a distributed ram using core generator in xilinx ISE

    actually I think I do it correctly because when I change the prefered language to vhdl and then use core generator it works.
    but I don't know the exact reason unfortunately.
    I hope someone could...
  7. Closed: Re: instantiate a distributed ram using core generator in xilinx ISE

    I checked https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgn_c_df_synthesize_verilog_design.htm

    but it was no special instructions for xilinx ISE to solve this problem.
    Can you...
  8. Closed: instantiate a distributed ram using core generator in xilinx ISE

    hello.
    I try to implement a distributed RAM using ISE IP core generator but I have this warning:

    WARNING:HDLCompiler:1499 - "E:\M.Sc\ISE projects\ipcore-test\test2\ipcore_dir\myram.v" Line 39:...
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    Closed: Re: word's length of single port RAM

    oh that was a mistake of copy paste.thats not the problem if you correct them and then run post simulate you can observe the problem. I changed the length to generate xst reports but I forgot to...
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    Closed: Re: word's length of single port RAM

    so what should I do?
  11. Replies
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    Closed: word's length of single port RAM

    hello.
    I have a verilog code for r single port ram :



    Code Verilog - [expand]


    1
    2
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    Closed: Re: using modelsim with tsmc 0.18u library

    your answer was convincing but I have another question,why gate level simulation is slow?
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    Closed: Re: using modelsim with tsmc 0.18u library

    I know Its not the best way but It can be useful to know the timing analysis approximately during simulation before synthesis.
    I have a pdf file that describes the area and delay of all gates in...
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    Closed: Re: using modelsim with tsmc 0.18u library

    but I saw somewhere that we can define other libraries for modelsim but I can't remeber.
    actually I'm not sure that it works for my case or not.
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    Closed: using modelsim with tsmc 0.18u library

    hello
    can anyone give me a hand about using modelsim with tsmc 0.18u library?
    I wanna use modelsim as my verilog code simulator and I wanna have timing analysis of my code in modelsim with tsmc...
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    Closed: how to fix WARNING:Xst:1710

    hello
    I'm trying to simulate a simple ROM(read only memory) in ISE 14.7 but unfortunately I have a warning during synthesize xst.

    WARNING:Xst:1710 - FF/Latch <data_out1_5> (without init...
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    [SOLVED]Closed: xilinx timing analyze using modelsim SE

    Hello
    I'm trying to simulate a simple D Flip Flop in xilinx 14.7.I've wrote the testbench and I set the modelsim as simulator an I did the behavioral simulation without any problem but when I try...
  18. Closed: verilog implementation of a viterbi decoder

    hello everybody.
    I'm trying to implement a viterbi decoder.
    I actually know the algorithm but I need to know the implementation techniques.
    could anybody introduce me an appropriate article or...
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