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Type: Posts; User: frankrose

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1. ## Thread: Problem of impedance matching of Gilbert cell mixer

by frankrose
Replies
1
Views
197

### Closed: Re: Problem of impedance matching of Gilbert cell mixer

Firstly, is it integrated or not? Integrated mixer's input is connected to a low noise amplifier (LNA) usually, matching between them is not necessary until the frequency is not too high and...

by frankrose
Replies
36
Views
637

### [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

In my opinion RMS is a fancy average calculation. The integral symbol and the division with a time period means the average calculation in the equation. The squared signal only relates to convert...

by frankrose
Replies
36
Views
637

### [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

Digital load current is like noise, as described in #5, and noise is characterized with its RMS value.
I agree with the difference, but SCR example is misleading now I think, or maybe it is answer...

by frankrose
Replies
36
Views
637

### [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

Hi,

Use RMS. It is the most talkative to estimate the load current with its all DC and AC components, and some overdesign is still necessary.
For example the voltage ripple on your LDO output...

by frankrose
Replies
20
Views
641

### [SOLVED]Closed: Re: PWM applied to load while current limiting on load simultaneously

If you know, that from fix DC 12V the current consumption is already too high why would you apply higher voltage?
BUCK and BOOST generate DC voltage with relatively small AC ripple, it is not...

by frankrose
Replies
20
Views
641

### [SOLVED]Closed: Re: PWM applied to load while current limiting on load simultaneously

Q1 in your current limit circuit is always switched off I think, doesn't look good.
Why don't you look for an IC? Basically you need a DCDC converter with adjustable output voltage and current...
7. ## Thread: OTA 2 stage (folded cascode + common source)

by frankrose
Replies
6
Views
420

### [SOLVED]Closed: Re: OTA 2 stage (folded cascode + common source)

M3 and M4 are not cascoded. They should be. Otherwise it won't work well.
Don't bias NMOS devices with PMOS diodes, it is a bad idea, they don't vary with process together.
8. ## Thread: Simple CMFB using two transistors only

by frankrose
Replies
3
Views
352

### Closed: Re: Simple CMFB using two transistors only

It seems extremely mismatch sensitive. The size or threshold difference generated error of the added devices is amplified by the folded cascode stage, I think it is not a practically viable solution.
9. ## Thread: Current Reference in Sub-Threshold region

by frankrose
Replies
3
Views
358

### Closed: Re: Current Reference in Sub-Threshold region

Extra circuitry doesn't need big consumption, rather area. And it is more effective.
10. ## Thread: Current Reference in Sub-Threshold region

by frankrose
Replies
3
Views
358

### Closed: Re: Current Reference in Sub-Threshold region

Probably it is possible to operate at the edge of the threshold voltage, but deep sub-threshold is not recommended becasue of worse matching between the circuit and the output current mirror....
11. ## Thread: Determining output impedance in LT SPICE

by frankrose
Replies
7
Views
404

### Closed: Re: Determining output impedance in LT SPICE

LTSpice is freeware, Cadence Spectre is the high-end, operating point reading of DC sweep is a luxury comfort I guess. Like AC stability analysis.
But with some struggling you can characterise...
12. ## Thread: Charge Pump with unity gain amplifier (Bootstrapping Charge Pump)

by frankrose
Replies
9
Views
565

### Closed: Re: Charge Pump with unity gain amplifier (Bootstrapping Charge Pump)

I don't see attachments...
13. ## Thread: What are biasing circuits?

by frankrose
Replies
2
Views
246

### Closed: Re: What are biasing circuits?

Bias circuit sets DC operating points of devices. It is necessary to reach good linearity, or fast operating speed. A simple base resistor can be bias circuit. And all above are true, if you use the...
14. ## Thread: Biasing an array of current steering DACs

by frankrose
Replies
6
Views
481

### Closed: Re: Biasing an array of current steering DACs

You can mirror the current with 128 branches. It won't be worse from mismatch and start-up viewpoints and actually the area will be smaller compared to cascaded NMOS/PMOS mirror stages.
If you want...
15. ## Thread: "Ideal" differential amplifier in SPICE

by frankrose
Replies
1
Views
227

### Closed: Re: "Ideal" differential amplifier in SPICE

With ideal source don't care about common mode voltage. Common mode DC is normally used to set operating point for input/output transistors, without devices it will increase the complexity. If you...
16. ## Thread: Fully-Differential folded cascode amplifier with enhanced gain

by frankrose
Replies
14
Views
930

### Closed: Re: Fully-Differential folded cascode amplifier with enhanced gain

Imagine that M5-M8 are simple cascode transistors, and the AUX-N/AUX-P set now the cascode bias voltages, which should be a Vgs+Vdsat for a folded-cascode amp with not enhanced gain to reach the...
17. ## Thread: Noise Figure budget analysis for power combiner & divider

by frankrose
Replies
4
Views
444

### Closed: Re: Noise Figure budget analysis for power combiner & divider

for every passive device the NF equals its own attenuation, so splitters have 3dB, and at combiners are not guaranteed the input signals are the same, thus they should have 0dB in that case I guess.

by frankrose
Replies
3
Views
324

### Closed: Re: DAC unit cap selection for SAR ADC

I am sad I don't have knowledge about it, it sounds interesting, but your equation seems vague in terms of left side / right side units.
I guess there are some extra behind them, which you...
19. ## Thread: How to take ESD and pad capacitances into consideration during design

by frankrose
Replies
1
Views
252

### Closed: Re: How to take ESD and pad capacitances into consideration during design

Connect them to ground, it is enough. ESD is normally at the direct input of the chip and builded into the pad between input & VDD/VSS, sometimes secondary ESD is implemented at the gates which are...
20. ## Thread: Analog Layout - Sharing source/drain

by frankrose
Replies
1
Views
317

### Closed: Re: Analog Layout - Sharing source/drain

1) not exactly true, useage of fingers has the advantage they need less area and the parasitics are smaller. disadvantage can occour when matching is the main viewpoint, with odd and small number...
21. ## Thread: [Cadence ADE XL] Optimize a Common Source Amplifier to 15dB gain via Corner Analysis

by frankrose
Replies
10
Views
571

### Closed: Re: [Cadence ADE XL] Optimize a Common Source Amplifier to 15dB gain via Corner Analy

I recommended you the section a) of below picture. The bias circuit is M3(diode connected) + the current source, the DC coupling device is R, and the AC coupling device is C. You should replace (or...
22. ## Thread: [Cadence ADE XL] Optimize a Common Source Amplifier to 15dB gain via Corner Analysis

by frankrose
Replies
10
Views
571

### Closed: Re: [Cadence ADE XL] Optimize a Common Source Amplifier to 15dB gain via Corner Analy

If you need 15dB DC gain above circuit is pretty useless, only at the ouput transition you have gain (derivate of your curves), which is input gate threshold voltage dependent, thus corner dependent....

by frankrose
Replies
4
Views
348

### Closed: Re: Modelling power supply for cadence simulations

VDC is ideal, through big part of the the full design phase it is should be enough. However if you know that your supply will be poor from any standpoint or your circuit is too sensitive it is...

by frankrose
Replies
4
Views
348

### Closed: Re: Modelling power supply for cadence simulations

These are package parasitics, not source model components. Source is not depending on the package, it should depend on what are you using as a source (LDO,battery,SMPS). And in the package the model...
25. ## Thread: Ring Oscillator Phase Margin Question

by frankrose
Replies
2
Views
210

### Closed: Re: Ring Oscillator Phase Margin Question

I guees you set wrong operation point for the stability analysis where the gain is negligible. Without more info hard to say correct answer...
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