Search:

Type: Posts; User: nand_gates

Page 1 of 20 1 2 3 4

Search: Search took 0.06 seconds.

  1. Closed: [moved] TCL/TK VGA GUI Demo module for Modelsim

    I have seen lots of peoples are looking for this.
    Following is what I have created for Modelsim 10.4 and tested
    its bit slow but works!
  2. Closed: Re: [MOVED] how to remove this error in xilinx

    memcoll [1]<=rxmemory [1]- 8'h20;
    temp<=memcoll [1];
    temp1[7:-temp]== uid[39:-temp];

    What I understand from ur code is temp and temp1 are 8 bit variables
    and this is what you want to do!
    case...
  3. Closed: Re: how to remove this error in xilinx

    Can you post the part of ur code here so that we can correct it and show you how to do it right?
  4. Closed: Re: Print screen statements in VHDL, need code explanation...!!

    You are right. write and writeline are taken from textio lib.
    By default PRINT_TIME is set to false because you dont want to print current time always .
    You can overwrite it to true if you want to...
  5. Replies
    4
    Views
    1,220

    Closed: Re: How to fix problem in my Verilog code

    Probably you want to add two numbers (BCD addition) and display them on 7seg displays.
    Here is the code I modified to do that.. Hope this helps!


    module...
  6. Replies
    14
    Views
    1,459

    Closed: Re: from verilog to vhdl code

    One possible not practical crude solution will be to use look-up table memory for each multiplication!
    Second approach will be use floating point /fixed point multiplier IP.
    Third approach use...
  7. Replies
    14
    Views
    1,459

    Closed: Re: from verilog to vhdl code

    Here it goes .....

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity md is
    port (
    clk : in std_logic;
    rst : in std_logic;
  8. Closed: Re: intel8085 designing

    Removed unused signal DBUF. Testbench added.

    module I8085(/*AUTOARG*/
    // Outputs
    RESETOUT, SOD, INTABAR, ADDR, S0, ALE, WRBAR, RDBAR, S1, IOMBAR, CLKOUT,
    HLDA,
    // Inouts
    AD,
    ...
  9. Closed: Re: intel8085

    Here I have converted gl85 vhdl model to verilog synthesizable RTL for 8085. I am glad to share with you all. Hope you will
    help me improving this one by posing bugs here.
  10. Closed: Re: A complete Intel Atom Cpu is synthesized on a FPGA

    I also wanted to read this doc! Thanks for uploading here!
  11. Replies
    1
    Views
    2,672

    Closed: verilog & clock & task

    Checkout this.............


    signal clk : std_logic := '0';
    clk <= transport not clk after 10 ns;

    constant RESET_TIME : integer := 8;

    signal reset : std_logic := '1';
  12. Closed: Re: Adder

    Checkout this..........

    module adder32(
    // Outputs
    result,
    // Inputs
    a, b
    );
    input[31:0] a;
    input[31:0] b;
  13. Closed: Re: help, basic vhdl state machine with nexus 2

    The problem could be ...
    You are using the push buttons B18, D18 and E18 without debouncing.
    Checkout this ...
    http://www.fpga4fun.com/Debouncer2.html

    Hope this helps!
  14. Closed: Re: help, basic vhdl state machine with nexus 2

    Can I get the complete vhdl code?
  15. Closed: Re: Please,help me!!!Verilog problems....in Xilinx

    Here is verilog code for 8 bit BCD counter

    module bcd_counter (clk, rst_n, count);
    input clk, rst_n;
    output [7:0] count;
    reg [7:0] count;
    always @(posedge clk or negedge rst_n)
    ...
  16. Replies
    5
    Views
    2,810

    Closed: Re: help:design compiler run out of memory

    What ur trying to flatten?? Do you understand how the flatten works?
    I think you need not go for 64 bit version of DC.
  17. Closed: Re: Pulse Generator Problem

    In verilog it's not required!
  18. Closed: Re: Pulse Generator Problem

    Here is the corrected code....

    module pulgen2 (
    reset_clk,
    out_clk,
    out_clk2,
    count_ena,
    count_clk
    ...
  19. Closed: Re: help, basic vhdl state machine with nexus 2

    Check out this one!


    process(clk)
    variable tal1, tal2: std_logic_vector(7 downto 0 );
    variable result: std_logic_vector(15 downto 0 );
    variable temp_operand: std_logic_vector(2 downto 0...
  20. Closed: Re: How to convert std_logic_vector to hexadecimal

    Check out this one!


    function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
    constant ne : INTEGER := (value'length+3)/4;
    variable pad : STD_ULOGIC_VECTOR(0 to (ne*4...
  21. Replies
    4
    Views
    1,418

    Closed: Re: RISC CORE

    Checkout this one....
    ftp://ftp.eecs.umich.edu/people/lefurgy/isc.tgz
  22. Closed: Re: Simulation with VHDL: How to create stimulus with Jitter

    You are on right track! That the way we generate clock with gitter!
  23. Closed: Re: What is RPS verification in System verilog

    Checkout this may be related to what ur looking for!
    vmmuser.org/wiki/images/4/42/XtremeEDA_VMM_for_Dummies.pdf
  24. Closed: Re: objets not found in questsim waveform window

    While compiling the code use +acc=rn switch.
  25. Replies
    2
    Views
    1,456

    Closed: Re: Help needed in writing FSM for ethernet.

    See the code below!
    Case statement for state = sadd is missing!



    module assembler (data, strt, eof, err2, clk, rst, buf_data, buf_addr);
    output reg [7:0] data;
    input strt,...
Results 1 to 25 of 500
Page 1 of 20 1 2 3 4