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  1. Replies
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    Closed: Re: Multiplexer output width depends on SELECT

    Hi,

    Thank you so much for your reply. Its really helpful. I tried implementing it in such a way that I have two back to back MUXs basically. So the output of the first MUX is of fixed width and...
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    Closed: Re: Multiplexer output width depends on SELECT

    Hi,

    I do have a single data bus. The size for it is fixed. But the data that comes on it changes in width. Basically its an unaligned data because of the additional information that is added to...
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    Closed: Multiplexer output width depends on SELECT

    I am implementing a MUX which basically selects which width of input data to use. Based on that, the output width of my MUX will change.




    input [width1-1:0] in1;
    input [width2-1:0] in2;...
  4. Closed: Re: Using calculated CRC as seed for the next CRC calculation

    Yes, my data bus is 256 bits. So i can only process 256 bits at a time. I need to do this over several iterations and keep using the previous CRC as the new seed. I dont think I will need any logic...
  5. Closed: Using calculated CRC as seed for the next CRC calculation

    We use seed as all F's when we calculate CRC. I have to work on a large data; which is broken down into slabs and fed to the CRC engine to calculate the CRC of that particular slab. Now this CRC...
  6. Closed: Re: Implementation of a MUX for selecting from 2 different sets of inputs

    Sorry. I will try to draw a circuit to explain myself better.
  7. Closed: Implementation of a MUX for selecting from 2 different sets of inputs

    I have to implement a design in which I have 2 sets of inputs. 1st set consists of different widths of inputs and another set consist of different set of a second input. These two will be selected...
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    Closed: Re: SystemVerilog Input generation

    Sure.
    I have modules : encoder, decoder, error (this flips random bits of data and sends it to the encoder which then sends it to the decoder which corrects the data).
    I havent used any clock. I...
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    Closed: Re: SystemVerilog Input generation

    Hi,

    I will make it simple. I have one error module that is injecting error. I have a for loop in that which allows it to inject errors at random locations over and over again. This works perfectly...
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    Closed: Re: SystemVerilog Input generation

    Thank you for your reply. So I am guessing I will have to add a clock to govern the two processes? Both the modules will execute, say on the positive edge of the clock. Is that correct?

    - - -...
  11. Closed: Re: Shifting control from one module to another iteratively

    Hi,

    Thank you for your reply. I had a query about incorporating a clock in the two modules. What if the two separate modules are run on a clock? Will that mean in one posedge of clock, the first...
  12. Closed: Re: Shifting control from one module to another iteratively

    Hi,

    I wish to have an input generator module that will generate data iteratively. Every time it generates a data, I want another module to perform a function on this data and send it to the DUT....
  13. Closed: Shifting control from one module to another iteratively

    I have two separate modules that iterate over a range. One generator module will produce input for DUT and this data goes to another module that works on this data iteratively. I tried to code this...
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    Closed: Re: SystemVerilog Input generation

    Thank you for your reply. The difficulty is that my testbench is performing another operation ; something of error injection. This module repeats for a few cyles. I want the generator to be a...
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    Closed: Re: SystemVerilog Input generation

    I do not need to test all the combinations. Say even 2^16 of the first combinations out of the 2^256. But in an increasing manner. How could I achieve that? Its basically to cover all cases while...
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    Closed: SystemVerilog Input generation

    I want to test my code which has a 256 bit input. I want my testbench to have a generator to generate a ramp input in order to test all possible input combinations but in a ramp fashion. What I mean...
  17. Closed: Re: $urandom for error insertion in Systemverilog

    Hi,

    This is the code with a seperate module. Here, every module is able to interact with each other and send data. The for loop in the error module produces different data with different error...
  18. Closed: Re: $urandom for error insertion in Systemverilog

    Hi Ads-ee,

    Thank you for your reply. I made a few changes in the code. I initially had a different module for error injection. Now I made it a part of the top test bench and directly connected to...
  19. Closed: $urandom for error insertion in Systemverilog

    Hi,

    I am making use of $urandom to insert an error in random bits of data. To begin with, I am inserting a 1 bit error, where the position bit is randomly chosen and flipped. I am new to...
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    Closed: Re: Error in Parity bits of Hamming Code

    Hi Ads-ee,

    Thank you for your reply. Yes, I am doing just that. I am using the code I have and giving it different combinations. I will come up with a conclusion. Thanks for all your help.
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    Closed: Re: Error in Parity bits of Hamming Code

    The very first link that you provided (https://codingvision.net/networking/hamming-error-correction-w-example), calls data+parity the syndrome (I am merely talking about the bit stream I get after...
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    Closed: Re: Error in Parity bits of Hamming Code

    Exactly!
    Update: the given method does not seem to work with SECDED. There is an extra parity bit here that XORs all the data and parity bits. This is causing an issue. I cannot just look at the...
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    Closed: Re: Error in Parity bits of Hamming Code

    Understood. I just want to detect an error in my parity bit, I do not want to correct it. So I am guessing this works. Also, when I test my code by changing one bit of parity, my final syndrome...
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    Closed: Re: Error in Parity bits of Hamming Code

    Hi Ads-ee,

    That makes a lot of sense. I was under the impression that if a parity bit is flipped, there will be a confusion whether its the parity bit thats in error or the data bit.
    But as you...
  25. Closed: Re: always_comb error in SystemVerilog code with case statement

    I am obviously not that stupid to run a SystmeVerilog code in a compiler that does not support SystemVerilog. And neither can I provide the entire code as it wont be necessary; the error is in this...
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