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Type: Posts; User: ashrafsazid

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  1. Closed: Re: Output of OTA with capacitor or without capacitor

    A good practice of designing OTA ( I assume here OTA, high output Z) is to keep the load as a non-dominant pole far from the dominant one which sets the gain and the BW. Following this, you will...
  2. Closed: Re: common source pole calculation vs. simulation

    You don't need to calculate like that using textbook approach. the total calculated gate cap is termed as Cgg, (or Cgs), check the opamp parameters attached.
  3. Closed: Re: common source pole calculation vs. simulation

    It seems there could be some issue on the method simulator follows to calculate the pole. I tried by myself and found a good match between hand calculation and simulator output. Here's using tsmc...
  4. Closed: Re: common source pole calculation vs. simulation

    What you are assuming, or the ground of hand calculation is simply RC based on the extracted DC. But the AC model of a particular technology is much complicated BSIM based model and could lead up to...
  5. Closed: Ratiomatric Error of Gain stage (say PGA)

    Hi,

    For many front-end systems (e.g. Wheatstone bridge) we need to measure only ratiomatric voltage. That means only the ratio as the signal. Now if the reference of the bridge varies, then is...
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    Closed: Re: Biasing folded cascode opamp

    If I understand correctly, if you see in the design I_mn3> (I_mp1+I_mp7), [so, I_mp3=2*I_mp1], that's only due to the leakage. "Ideally" I_mp1 = I_mp7 for a folded-cascode can be employed. But if...
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    [SOLVED]Closed: Re: reading a file in verilogA

    Found the issue, it is related to the filesystem difference between Unix and Windows text format. The difference of "Line end Character" which has to be a newline (\n) creates the issue.
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    [SOLVED]Closed: reading a file in verilogA

    Hi,

    I need some helps regarding reading a file (say .txt, could be .csv as well) from a directory path and then generate a voltage signal based on the array of values from the file.

    There is a...
  9. Closed: Re: Sidelobes from Periodic AC (pac) Analysis

    I meant Sidebands.
  10. Closed: Sidelobes from Periodic AC (pac) Analysis

    Hi,

    Is it possible to get an ac transfer curve of a sampled system with all desired sidelobes? I did a pac analysis of SC filter with 20 sidebands and found the behavior like this. But I am...
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    Closed: Re: cmfb - creation cm voltage

    The CMFB compares between your "output common mode" and "desired common mode" and feeds back a negative signal for regulation. The desired CM voltage you can generate by using a resistive divider...
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    Closed: Re: 2 Stage Opamp with SC CMFB

    The CMFB used to give a separate DC CM gain at the output. Here you are sensing second stage output (which is indeed the "main" output) and regulating "any" internal bias node on a negative...
  13. [SOLVED]Closed: Re: Loop Gain Phase issue for the OpAmp with Class AB output stage

    Hi Frank, Yes it is working expected with source-bulk shorted. But the DC gain decreases indeed, around 20 dB!
  14. [SOLVED]Closed: Loop Gain Phase issue for the OpAmp with Class AB output stage

    Hi,

    I am confused about the phase shift at DC for the stb analysis of a Class AB op amp shown in figure below. Please note the input and output polarity.

    149378

    I put the op amp in negative...
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    Closed: Re: Howland Current Circuits

    This is the Article.
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    Closed: Howland Current Circuits

    Hi,

    on an old article I came to know about this Howland Circuit. It was mentioning improved howland vs. original howland circuit. Is the resistor R4 is the difference between them? Is the function...
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    Closed: Re: Ear headphone with low sound

    Interested to know the mapping between these two pictures. Is differential Input of 0.7V is mapped to Left/Right of the universal 3.5mm Jack?
  18. Closed: Re: Differential amplifier with active load

    Changing W of "only" M4 will not keep the topology differential any more. But if you change the width of the active load pair of M3-M4 you are driving them with more gm, or pushing them to low vdsat,...
  19. Closed: Re: Fully Differential Opamp - Folded Cascode + Common Source SC CMFB Issues

    You can use the same clock for both of the stages if they are both fully differential. In this case, you may need 10-15 clock cycles to set up the desired common mode. This is dependent on the SC...
  20. Closed: Re: Operational Transconductance Amplifier

    you can say this is a two-stage sense amplifier. The cross-coupled diode-connected load are multiplied as a current amplifier on the second stage. the two "extra" nmos are placed to increase the...
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    Closed: Re: Cadence ADEXL Monte-Carlo Data Processing

    148179

    Even running Ocean-XL from CIW window has the same issue.
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    Closed: Re: Cadence ADEXL Monte-Carlo Data Processing

    Tried with CIW but not sure what is going on, I do not see any log file or any sign of running. What is the command to run it from Linux terminal?


    I think it is not available on my package, I...
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    Closed: Re: Cadence ADEXL Monte-Carlo Data Processing

    Thanks. I see the OCEAN-XL can be generated from ADE-XL itself, as I showed you here. Is there anyway to run that OCEAN script apart from ADE-XL? (e.g. from terminal or anywhere?)
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    Closed: Re: Cadence ADEXL Monte-Carlo Data Processing

    Monte Carlo simulation does not support variable sweep. This what I get when I try it. I am not familiar or do not know so good about Ocean script writing.

    148177



    Does Monte-Carlo sampling...
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    Closed: Re: Cadence ADEXL Monte-Carlo Data Processing

    Probably I did the same way you suggest. Providing temperature on Corner and then sweeping them creating multiple corners. Heres the image:

    148172
    148173


    This is the Ocean Script:
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