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Type: Posts; User: dick_freebird

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  1. Closed: Re: What's the difference between stacked and cascode configurations?

    I would call this figure a double-cascode, one FET is actively
    driven and the others have static gate bias.

    If you look at RF CMOS switches, those are stacked and all
    of the gates are...
  2. [SOLVED]Closed: Re: LM741 Amplifier not working with IR2110 IC [PROTUES]

    I think you'd be much better off with a simple level-shifter
    logic gate (believe IR2110 accepts standard 5V "TTL" inputs).

    Op amp like 741 will have very slow output slew rate and
    there might be...
  3. Closed: Re: Oscillator jitter transient simulatin in spectre

    Measuring is fine, but first you have to induce the jitter.

    A determinstic jitter may reveal itself if your schematic
    has enough realism (couplings and edge alignments).

    A random jitter...
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    Closed: Re: Zero threshold MOSFET design

    One possible option could be "FET-quad mixers" which I have
    seen made of zero-VT devices, 4 in a bridge. But these tend
    to be made for 50-ohm systems and low-ish insertion loss at
    that...
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    Closed: Re: Zero threshold MOSFET design

    If you're talking about the "design" of a transistor species in
    a foundry flow, that's really more process design than device.
    The norm is that "zero-VT" (aka "native") devices share the
    same...
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    Closed: Re: Cannot find vdd in the design

    In many standard cell libraries, supply rails are not shown as
    wired pins, but embedded as global named nets in the lowest
    level schematic (if schematics exist at all, in that library) or
    in the...
  7. Closed: Re: Looking for SPICE model for coupled lossy transmission line

    I'd be happy to find just one tline .model that seemed credible.
  8. Closed: Re: How to reduce Harmonic Balance simulation time in Spectre

    Minimizing the number of distinct nodes and devices is key.

    At my last employer they struggled with this too, and got a
    lot of improvement by having one of the CAD group folks write
    a Perl...
  9. Closed: Re: Help in understanding the paper "Understanding Wide-band MOS transistors"

    Re 2: There is always a technology gain-bandwidth product
    which is your ultimate limit, even if you've done your best
    with the rest of the circuit optimization.

    A lineup that uses (say) one...
  10. Closed: Re: SMD component fixture for antenna matching prototyping

    There exist antenna-tuning (matching) RFICs, I saw this going
    on at the last "straight job" employer (although it was way
    outside my activities & interests). Can't help you with selection
    or...
  11. [SOLVED]Closed: Re: calculating capacitance of transistor gates

    Total gate charge is useful to calculate switching losses
    but treating it as a fixed capacitance will not be accurate
    when it comes to transient switching behavior. Be sure
    you want the right...
  12. Closed: Re: Obtaining D flip-flop mosfet-level schematics from CMOS layout

    That looks like a private "tutorial" library for a specific
    college course.

    What do you find under the FreePDK? Any schematics
    at all? Maybe a DFFRNQ (dffrnq) minus the "X1" (which
    looks to be...
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    Closed: Re: Layout problem when trying to see layers

    Yes, because you are trying to see "stuff that isn't there"
    (or, stuff that isn't anywhere Cadence knows to look).
    Do what I told you. Property-edit the "X" blocks, see
    what they are and where...
  14. Closed: Re: Obtaining D flip-flop mosfet-level schematics from CMOS layout

    I suppose somebody -could- hand-trace all the connections
    and provide you a schematic, but since it's a "Free" PDK
    why not just go grab a copy and ***** open the cell
    library? Have you...
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    Closed: Re: Layout problem when trying to see layers

    Those boxes with "X" fill are saying that it can't
    find the contents.

    Property-edit them, see what library it thinks it's
    looking for, then check your library list (Library
    Manager) and see...
  16. Closed: Re: Pool Saltwater Chlorine Generator - PCB Help Needed

    Salt water chlorine generators have to throw a lot of
    current to be useful. If that thermistor is in the power
    path and is responsible for inrush current limiting, it's
    got a hard life ahead of...
  17. Closed: Re: Why is pmos and nmos put vertically and not side by side(horizontally)in ic layou

    I have yet to work in any technology that's so constrained, but
    I've sat through presentations about it.

    "Back in the day" it was all just about maximum logic cell density.
    And that is usually...
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    Closed: Re: obtaining thermal rise in diode

    We call this "sandbagging the spec". Conservative only costs
    the customer money but tends to keep them safe; aggressive
    makes field returns and ruins AOQ statistics.

    There is also that diode...
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    Closed: Re: NMOS LDO current sense circuit help

    So, given that this is an internal application, who is making
    the current sense a requirement, and what are the required
    attributes?

    If the output is not exposed, or only exposed to a local ...
  20. Closed: Re: Synchronous Buck Converter FET selection

    Are you simulating this design? Shoot-through can be seen
    in the drain currents' overlap. Switching losses can be taken
    from terminal voltages and currents.

    I would not bother calculating if the...
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    Closed: Re: NMOS LDO current sense circuit help

    You might compare PMOS pass FET to {NMOS pass FET
    plus charge pump actives and caps} - "solution size", not
    just the pass FETs.


    Current sense accuracy matters little in current mode ...
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    Closed: Re: NMOS LDO current sense circuit help

    You might use the metal run from pass FET source to
    pad(s) as your sense resistor.

    It will be difficult or impossible to get a good current mirror
    fidelity with so little headroom, and your...
  23. Closed: Re: Op-amp design specification for certain application

    "Accurate" closed loop gain wants some care, as the
    GBWP is usually the -3dB point - where gain has rolled
    off by 30% or so. That's not "accurate" really. You will
    want some excess GBWP if you...
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    Closed: Re: High Frequency using 8051

    You might just like a large MOSFET gate driver without
    the discrete FETs, depending on the (not-stated) load
    current, rise/fall times and tolerance of the part to
    inductive over / undershoots....
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    Closed: Re: Varactor C-V Curves In Cadence

    I would do a transient analysis with a pulsed current source
    and a trivial shunt (like 1E12 explicit resistor). I=CdV/dt, use
    fixed (after initial condition=0) flat-top I, your C(V) is the ...
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