Search:

Type: Posts; User: johnz

Page 1 of 2 1 2

Search: Search took 0.02 seconds.

  1. Replies
    4
    Views
    1,649

    Closed: Re: How to deal with memory in a processor?

    In general project, you can use memory compiler to generate memory,
    But, for a processor, should use full_custom design to implement high-density and high speed, low power.
  2. Replies
    3
    Views
    1,091

    Closed: Re: FE and FB view in physical design

    backend view include lef, milkway, spice, cdl file for lvs, sometimes even has gds file.

    eda tools cannot do physical design without backend view.
  3. Replies
    5
    Views
    1,401

    Closed: Re: timing analysis

    This is a cell delay.

    cell reference name is "AOI21X1"
    cell instance name is "DTMF_INST/ULAW_LIN_CONV_INST/i_150"
    Delay type is absolute, not incremental.

    The max 0->1 delay from A0 pin to Y...
  4. Replies
    6
    Views
    1,557

    Closed: Re: How to call C tasks in Verilog source codes?

    can take look this book:
    The Verilog PLI Handbook : A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface

    there are some example in this website:...
  5. Replies
    7
    Views
    1,375

    Closed: Re: SDF file and slk file

    use less in linux or unix.
    less is faster than vi when open big file.
  6. Closed: io timing analysis

    you must take account clock insertion delay for analysis of IO timing.

    to over-constrain boundary logic, margin should be added to input delay and output delay, clock uncertainty don't represent...
  7. Replies
    8
    Views
    1,339

    Closed: Re: set up & hold

    I think best one is Prime Time user guide.
  8. Closed: Re: How do I get more hold time slacks after PAR with Astro.

    Hi wkong_zhu,
    I can try PC and PKS to do post-routing optimization, using best case library , setting minimium wire length and slack criteria.
  9. Replies
    7
    Views
    1,909

    Closed: Re: Does Cadence PKS is a good software?

    I have used PKS for one year and employ it to place, it is not bad.
    But more people use PC. I don't compare them.

    placement of SOC encounter is more powerful, PKS documents cadence release are...
  10. Replies
    14
    Views
    11,681

    Closed: Re: Tools for Static Timing Analysis

    both Prime time and Celtic have Static Timing Analysis engine.
    For now, Prime time is more popular.
    But below 0.13 um, analysis of cross-talk is very important, Celtic is good at that.
  11. Replies
    7
    Views
    1,827

    Closed: Re: How can I solve this?

    hi,johnz,
    Are u sure this can lead to the synthesis of a dff and an adder?[/quote]

    Hi laglead,
    I just want to try another coding,
    you can thynthesize it by yourself, take look whether...
  12. Replies
    38
    Views
    17,753

    Closed: Re: how to place & route in CADENCE?

    can take look some tutorials in soc encounter direction like that encounter_installation_direction/etc/share/~ .
  13. Replies
    7
    Views
    1,827

    Closed: Re: How can I solve this?

    maybe can try this:

    always @(posedge clk)
    if(wb_cyc_i) cyc_cnt <= cyc_cnt + 1;
  14. Replies
    1
    Views
    1,683

    Closed: how to merge multiple SDC

    Hi ,
    recently, I do physical synthesis. there are five sdc files for two functional modes and three test modes.
    I want to get a mixed and closer sdc used by physical syntesis tool , such...
  15. Replies
    1
    Views
    2,260

    Closed: Re: assign statement in netlist

    Hi,
    two reasons cause assign statement in netlist.
    1. two or more poort connected to same net.
    2 . a port directly connected to 1'b0 or 1'b1

    you can try:

    for PKS 5.2 :

    set_global...
  16. Replies
    5
    Views
    6,188

    Closed: Re: CMOS ???????

    most of design, for now, employ CMOS, even analog design.
  17. Replies
    10
    Views
    1,839

    Closed: Re: How to do Scan Synthesis?

    compile -scan
  18. Replies
    10
    Views
    1,850

    Closed: Re: Effects of low Vt..

    0.13um technology and technology under 0.13um have bigger percentage of leakage power. multiple Vt std library( low, normal, high Vt) are used for reducing leakage power .

    They have same area.
    ...
  19. Replies
    0
    Views
    997

    Closed: how acroread support Japanese in Linux?

    as title
  20. Replies
    4
    Views
    1,398

    Closed: Re: analog power ring

    analog power ring let core (digital) is free from noise from analog part.
  21. Replies
    5
    Views
    3,757

    Closed: analog ic design career in japan

    many companies in Japan are good at designing big digital IC, they prefer to buy analog IP.
  22. Closed: Re: how to design a PCM-PWM converter for audio PA?

    you can take look datasheet of chip produced famous company. for example, freesclae 's dragon ball.
    there are some description in PWM part.
  23. Replies
    1
    Views
    1,172

    Closed: Re: how is mcu dpartment of freescale in China?

    In zhuzhou, It is said freescale is not bad, but many people don't want to be in zhuzhou.
  24. Closed: Re: SRAM again

    area of two 1k sram is bigger than 2k sram due to increase of line and column decode logic.
  25. Replies
    4
    Views
    1,715

    Closed: Re: help: about netlist extraction.

    why convert to verilog. what is format of layout, what is format of netlist extract from layout.
Results 1 to 25 of 38
Page 1 of 2 1 2