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TrickyDicky,

The solution with the constant worked.
But what if x was an array of integers ?

type array_1d_integer is array ( integer range <> ) of integer ;
Can you post an example of a null...

Sorry.
I viewed this on my cellphone first.
And what you wrote in the line of code didn't show.

Forum admins - please note of this problem.
A snapshot of how this looks on my phone is...

This is what I tried to do.
But how will the definition of that constant look?
Please show an example.

Hello,

In a package I have the following definition of a unconstrained unsigned array:

type array_1d_unsigned is array ( integer range <> ) of unsigned ;
In another file I have an input port...

This question is about writing "optimization friendly" VHDL code.
Suppose my application requires adding 2 numbers and then using the result for another 2 seperate additions.
Possible ways to write...

Thanks,
Is it possible to force an integer to be less then 32 bits long ?

Hello,

This is the definition of the "numeric_std" multiplication function ( '*' )

-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype:...

Try to declare the component prototype of "Reset_Delay" in the .VHD file where you instantiate it - instead of instantiating it from work.reset_delay.

Hi,
It'll be easier to understand what you're proposing if you post a code example.

When was the last time you tried it ?

They do have a template that makes use of a shared variable - but it's for a "True Dual-Port RAM with a Single Clock"....

Hello,

Taken from this link:
https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/vhdl/vhd-single-clock-syncram.html

The following...

Hello,

I have an Avalon MM interface of which I'm the master.
The data that I want to write to the slave is buffered in a FIFO.
To achieve better timing - I want to use a FIFO with a registered...

Regarding your question.
Comparing VHDL and OpenCL as 2 languages is misleading.
OpenCL is MUCH more then just a "Higher Level" language. It's a complete framework that describes communication...

So if we examine the TLP layer messages running over the PCIe link - we'll usually see the NIC's hardware asking for data from the South Bridge and the South Bridge responding to it ?
As opposed to...

My question is about data transfer between a PCIe peripherial and system memory. Example: Suppose we need to send a big chunk of data ( stored in system memory ) over an Ethernet network.

How will...

At 100MHz - why do you want to use a SERDES ?
Why not implement a simple synchronous interface (like SPI) ?

What is your communication protocol ?

Yes.
The "bitslice" is an IOSERDES, IODELAY and FIFO aggregated into one primitive.
Before Ultrascale - series 7 had these separately.

The new approach is what Xilinx calls: "Native Mode".
The...

In essence - "link training" is the process of finding the safest sampling point at receiver to avoid timings violations and achieve a robust link.
In the Ultrascale family the recommendation is to...

So it should fail during p&r ?

If it was then driving x<='0' would also reset y (18) ??
Why would anyone write such code?? It "hides" logic and hurts the readability...

And what if Y was driven by another process of the same architecture ?
Will this be legal ?

Hello,

While debugging an old design I came across the following code:


alias x : std_logic is y ( 18 ) ; -- y is a 32 bit wide std_logic_vector input port.

begin

process ( clock ) is

Hello,

What does the VHDL '|' (like bitwise or in C) operator do ?

Yes. Waiting to hear back...