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  1. Replies
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    Closed: Re: Assigning a null array in VHDL

    TrickyDicky,

    The solution with the constant worked.
    But what if x was an array of integers ?

    type array_1d_integer is array ( integer range <> ) of integer ;
    Can you post an example of a null...
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    Closed: Re: Assigning a null array in VHDL

    Sorry.
    I viewed this on my cellphone first.
    And what you wrote in the line of code didn't show.

    Forum admins - please note of this problem.
    A snapshot of how this looks on my phone is...
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    Closed: Re: Assigning a null array in VHDL

    This is what I tried to do.
    But how will the definition of that constant look?
    Please show an example.
  4. Replies
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    426

    Closed: Assigning a null array in VHDL

    Hello,

    In a package I have the following definition of a unconstrained unsigned array:

    type array_1d_unsigned is array ( integer range <> ) of unsigned ;
    In another file I have an input port...
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    Closed: Logic duplication and optimization

    This question is about writing "optimization friendly" VHDL code.
    Suppose my application requires adding 2 numbers and then using the result for another 2 seperate additions.
    Possible ways to write...
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    Closed: Re: VHDL integer to integer multiplication

    Thanks,
    Is it possible to force an integer to be less then 32 bits long ?
  7. Replies
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    Closed: VHDL integer to integer multiplication

    Hello,

    This is the definition of the "numeric_std" multiplication function ( '*' )

    -- Id: A.15
    function "*" (L, R: UNSIGNED) return UNSIGNED;
    -- Result subtype:...
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    Closed: Re: ERROR:HDLParsers:709

    Try to declare the component prototype of "Reset_Delay" in the .VHD file where you instantiate it - instead of instantiating it from work.reset_delay.
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    Closed: Re: Inferred VHDL dual port RAM template

    Hi,
    It'll be easier to understand what you're proposing if you post a code example.
  10. Replies
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    665

    Closed: Re: Inferred VHDL dual port RAM template

    When was the last time you tried it ?

    They do have a template that makes use of a shared variable - but it's for a "True Dual-Port RAM with a Single Clock"....
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    Closed: Inferred VHDL dual port RAM template

    Hello,

    Taken from this link:
    https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/vhdl/vhd-single-clock-syncram.html

    The following...
  12. Closed: Avalon MM - using a FIFO with a registered output

    Hello,

    I have an Avalon MM interface of which I'm the master.
    The data that I want to write to the slave is buffered in a FIFO.
    To achieve better timing - I want to use a FIFO with a registered...
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    Closed: Re: OpenCL vs VHDL running in FPGA

    Regarding your question.
    Comparing VHDL and OpenCL as 2 languages is misleading.
    OpenCL is MUCH more then just a "Higher Level" language. It's a complete framework that describes communication...
  14. Closed: Re: How is data transferred from memory to PCIe cards?

    So if we examine the TLP layer messages running over the PCIe link - we'll usually see the NIC's hardware asking for data from the South Bridge and the South Bridge responding to it ?
    As opposed to...
  15. Closed: How is data transferred from memory to PCIe cards?

    My question is about data transfer between a PCIe peripherial and system memory. Example: Suppose we need to send a big chunk of data ( stored in system memory ) over an Ethernet network.

    How will...
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    Closed: Re: Link Training with IO DELAY

    At 100MHz - why do you want to use a SERDES ?
    Why not implement a simple synchronous interface (like SPI) ?
  17. Replies
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    1,104

    Closed: Re: Link Training with IO DELAY

    What is your communication protocol ?
  18. Replies
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    1,104

    Closed: Re: Link Training with IO DELAY

    Yes.
    The "bitslice" is an IOSERDES, IODELAY and FIFO aggregated into one primitive.
    Before Ultrascale - series 7 had these separately.

    The new approach is what Xilinx calls: "Native Mode".
    The...
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    Closed: Re: Link Training with IO DELAY

    In essence - "link training" is the process of finding the safest sampling point at receiver to avoid timings violations and achieve a robust link.
    In the Ultrascale family the recommendation is to...
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    Closed: Re: Parent signal when alias is accessed

    So it should fail during p&r ?
  21. Replies
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    1,564

    Closed: Re: Parent signal when alias is accessed

    If it was then driving x<='0' would also reset y (18) ??
    Why would anyone write such code?? It "hides" logic and hurts the readability...
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    Closed: Re: Parent signal when alias is accessed

    And what if Y was driven by another process of the same architecture ?
    Will this be legal ?
  23. Replies
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    Closed: Parent signal when alias is accessed

    Hello,

    While debugging an old design I came across the following code:


    alias x : std_logic is y ( 18 ) ; -- y is a 32 bit wide std_logic_vector input port.

    begin

    process ( clock ) is
  24. Replies
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    Closed: Unfamiliar VHDL | operator

    Hello,

    What does the VHDL '|' (like bitwise or in C) operator do ?
  25. Replies
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    Closed: Re: VHDL unconstrained array in VCS

    Yes. Waiting to hear back...
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