Search:

Type: Posts; User: avadak

Search: Search took 0.00 seconds.

  1. Replies
    5
    Views
    563

    Closed: Re: MOSFET Speed and power tradeoff

    Dear circuitking,
    the range of the MOS operating region can be determined by gm over Id ratio (gm/ID=2/(VGS-VT)). Hence, if gm is in the range 5-10 S/A the MOS operates in strong inversion, the...
  2. Closed: Re: Input and output matching in Distributed amplifier

    Dear circuitking,
    with discrete component I indicated the off-chip components (the SMD components). In your case I suggest to design an inductor. Even with 50 GHz the wavelength is too big for IC...
  3. Closed: Re: Input and output matching in Distributed amplifier

    Yes theoretically you can substitute the inductor with the transmission line but, as explained in post #4, in IC design the trace lengths are too small to implement the transmission lines at low...
  4. Closed: Re: Input and output matching in Distributed amplifier

    Dear circuitking,
    your procedure is correct, but the synchronism condition must be take in account. To guarantee the same time constant on the drain and the gate lines LgCg = LdCd. In traditional...
  5. Closed: Re: Input and output matching in Distributed amplifier

    Dear circuitking,
    the design of a distriubted amplifier is quite different from the traditional CS amplifier. It comprises several mosfests (3-5) connected with two transmission lines: one for the...
  6. [SOLVED]Closed: Re: Can you help me with this Verilog to VHDL translation?

    Dear Ironlord,
    I'm not known the verilog language but you have to pay attention on these two code lines:

    cur_inputs<=switches;
    last_inputs<=cur_inputs;

    in VHDL you are defined cur_inputs and...
  7. Closed: Re: Dimensions for microstrip quarter wave transformer

    Dear Friend,
    the dimensions of a quarter wave transformer depend on two main paramenters: the impedence to match and the dielectric characteristics. Supposing to match an impedence Zin and the load...
  8. Replies
    7
    Views
    463

    Closed: Re: transistor state in cadence vertuso

    Dear Junus,
    the saturation region depends on the gm over ID ratio that is equal to 2/(VGS-VTH). The weak inversion occours for gm/Id in range 15 - 25 S/A. Probably in your case with 60 mW you don't...
  9. Replies
    0
    Views
    483

    Closed: Distributed Amplifier Layout

    Dear Sir,
    I'm designing my first analog layout. In particular I'm designinng a conventional four stages Distributed Amplifier with SG13S process. When I introduce the inductors in the layout, I...
  10. Replies
    2
    Views
    966

    Closed: Re: lna layout problem in cadence

    Hi Avinash, the RF layout are very complicated. There are a series of techniques for minimizing the parasitics of the circuit. However the book "the art of analog layout" of alan hasting is a good...
Results 1 to 10 of 10