Type: Posts; User: TonyLS

Page 1 of 2 1 2

Search: Search took 0.02 seconds.

  1. Replies

    Closed: Re: Lockup Latch for DFT purpose

    I do not believe that your statement is correct. Lock-up latches will work between two async clock domains within the scan path. Refer to my original post. The clock of the lock-up latch is CLK1...
  2. Replies

    Closed: Re: Lockup Latch for DFT purpose

    Lockup latches are placed in the scan-path (Q to scan_data_in), not in the functional path. It is used to reliably transfer scan_data in between clock domains during scan shifting.
  3. Replies

    Closed: Re: power analysis using synopsys DC compiler

    Use the -instance and possibly the -target arguments to the read_saif command to push down to the same level of hierarchy that is used by dc_compiler for synthesis.
  4. Replies

    Closed: Re: Lockup Latch for DFT purpose

    Lock up latches allow you to have flops on multiple clock domains in the same scan chain. Flops of the same clock domain will be grouped together separated by a lock up latch.
  5. Replies

    Closed: Re: Serial scan patterns are failing

    Seems to be something wrong when scanning in data during scan in shift mode of the serial patterns. Either incorrect scan stitching, scan-clock, or most likely hold time issues during scan shift....
  6. Replies

    Closed: Re: LEC between two netlists

    I can't comment exactly without knowing the details of your design/mems. But the premise behind doing LEC between pre and post scan inserted netlists is to confirm that the functional design between...
  7. Replies

    Closed: Re: LEC between two netlists

    You want to be sure that the scan path is not active on the revised netlist. Tie-off the top level scan-mode and scan-enable control pins.
  8. [SOLVED]Closed: Re: How to load an already compiled design in Design Compiler?

    Shouldn't the constraints be contained within the ddc? I think most are. But it's possible that the timing_derate contraints are not contained in the ddc. If anyone can confirm this please comment....
  9. Closed: Re: How do I synthesize an inout port using DC?

    You can use both an INPUT delay constraint for the input side and an OUTPUT delay constraint for the output side
  10. Replies

    Closed: Re: Design Compiler Command Needed

    I use:
    report_clock_tree -to path/flop/CLK
  11. Replies

    Closed: Re: Bottom up synthesis using dc compiler

    1) Yes, you need to write out the ddc or verilog version of each of the submodules that you have compiled.
    2) The top level will be a verilog file that instantiates the submodules. The submodule IO...
  12. Replies

    Closed: Re: synthesis question about generated clocks

    If you do nothing wouldn't dc_compiler time the corresponding registers with both clocks?
  13. Closed: Re: set_disable_timing constraint using wildcards not working

    I'm using dc_compiler. I'm sure there is a way in TCL to obtain a list of pins of the memory cell, filter the applicable ones and apply them to the set_disable_timing command. I'm not that proficient...
  14. Closed: set_disable_timing constraint using wildcards not working

    Hi all,

    I'm trying to use wildcards to disable timing arcs between the functional address pins, ADDR*, of a memory and the test clock of the memory, TCLK.

    Multiple address pins using a...
  15. Closed: Want formality run and keep boundary optimization turned on in synthesis

    I am synthesizing with boundary optimization set. The RTL to Netlist formality run has 32 failures. All from the same 32 bit bus. During debug I noticed there is an inversion (additional inverter in...
  16. Closed: dc_compiler: setting input_delay and output_delay for feed through paths

    I have many paths that start at an Input pin, goes through combo logic, then to an Output pin. What complicates things is that the Input can fanout to a flop as well as an Output. Also the Output can...
  17. Replies

    Closed: Re: Compile ultra problem in dc shell

    The problem you are having doesn't show up as a hard Error. Search for "Cannot find" or "LBR-1" within the log file.

    These searches should provide the design name that the linker is expecting but...
  18. Closed: Can dc_compiler auto black box modules that are not available?


    Is there a switch that can make dc_compiler auto black box modules that are not available? I know that dc_exployer and primetime auto black boxes but can't seem to find the command to enable...
  19. Closed: Formality: Reading in an existing match-point file


    To save on run time I would like to read in an existing MATCH point file that was created by Formality. I'm hoping that FM will see that the points have already been matched and not go off and...
  20. Closed: dc_compiler: create_generated_clock from a generated clock?

    What are the negative effects if any of generating a clock from a previously generated clock? Both of which will use the create_generated_clock command.

    The following is mentioned in the...
  21. Replies

    Closed: Conformal CDC, checking synchronizer resets

    Does anyone know how or if conformal cdc can check that the reset signal going to a synchronizer is on the same clock domain as the clock of the synchronizer?

  22. Replies

    Closed: How to report flops by hierarchy

    Does anyone have a handy way of reporting a list of flip flops by hierarchy in DC? I'm looking to do it interactively in DC while the ddc is loaded.

    Thanks for your help
  23. Closed: How to change sub-module port tie off value in test compiler

    There's a sub-block in my design that I receive from another group which has two test ports tied to 1'b0. Within my scan insertion script (using test compiler within dc_compiler) which uses the ddc,...
  24. Closed: Re: dc_compiler: How to change a Warning message to an Error message

    I think VER-735 has to do with a VERilog coding warning, not the version of dc_compiler

    The following is part of the man page on VER-735:

    VER-735 (information) %s Variables...
  25. Closed: dc_compiler: How to change a Warning message to an Error message

    Does anyone know how to change a Warning message for a particular warning# to an Error within dc_compiler?
    I know how to suppress warnings, but can't find a command to change a warning to an error. ...
Results 1 to 25 of 49
Page 1 of 2 1 2