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Type: Posts; User: timof

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    Closed: Re: Metal Oxide Semiconductor in strong Inversion

    Robotduck -

    These are classical C-V curves of MOS structure, having nothing to do with traps or interface defects.
    See classical books by S.Sze or E.Nicollian.
    This is a standard response of a...
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    Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    This video shows, approximately, how does layout for 7nm technology look like:

    https://www.youtube.com/watch?v=6xqx1-XOCv0
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    Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    If only doing real FinFET design layouts - with all their constraints, parasitics bottlenecks, complexity of multi-patterning, nonlinear effects, etc. etc. - would be that simple...

    "I know...
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    Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    Yes, agreed, the layout still contains polygons.
    But, if you look at the FinFET layout (devices with interconnects), you can tell immediately it is not a planar CMOS technology.
    The style is...
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    Closed: Re: Abbreviations of Layers in 65nm LSW

    Most of the layer names in TSMC PDKs are actually quite easy to understand - like M1, via1, etc.

    If you have questions on layers whose names are not obvious, you can check with the design rule...
  6. Closed: Re: Need documets related to extraction of Inductance using Cadence Assura

    Unfortunately, the capacity of EM (Electromagnetic) solvers is not so high.
  7. Closed: Re: Optimized MinCap, Minres values for 10 MHz amp simulation using Spectre

    You should be very careful with parameters like minres and mincap - read the manual, how extraction tool you are using handling them.

    For example, minres can cause extraction tool to "drop"...
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    Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    There are actually quite a lot of unusual and even counter-intuitive effects with FinFETs and with interconnects / parasitics in FinFET technologies.

    For example, gate resistance may go up as gate...
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    Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    The best resources are documents and training materials from the foundries.
    Which is foundry proprietary and confidential.
    Meaning - you can see that only on the job, working for one of the...
  10. Closed: Re: What are the layout methods to make source to drain capacitance zero?

    The layout method to reduce coupling capacitance is shielding, or screening.
    Net A placed between nets B and D reduces coupling capacitances between B and D.
    A structure that completely shields an...
  11. Closed: Re: Need documets related to extraction of Inductance using Cadence Assura

    Well, first of all, Assura RCX is an outdated or deprecated extraction tool.
    It was replaced by QRC then Quantus, by Cadence.

    Quantus QRC can extract inductances, but you need to tell it...
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    Closed: Re: Rplpoly layout matching problem

    Can you show the layout and the (post-layout) netlist?
  13. Closed: Re: What is the difference between LVS and ERC ?

    To extend a little bit (or to give examples of checks) on what erikl already explained:

    * LVS (Layout Versus Schematic comparison) - does the following things:

    - net connectivity extraction...
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    Closed: Re: mosfet as a switch in 28nm technology

    Are you asking about a book on layout in general, or on power transistor layout?
  15. Closed: Re: Looking for 'Introduction to CMOS OP-AMPs and Comparators' ebook

    Analog design in advanced nodes (such as 10nm, 7nm, 5nm) is VERY different form older nodes in this sense - layout parasitics in older nodes were second order effect, and devices were playing the...
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    Closed: Re: Parasitic capacitor extraction: huge value

    You show schematic only, but talk about parasitic capacitance.
    Is this schematic simulation problem, or post-layout?
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    [SOLVED]Closed: Re: layout extraction changing device

    Try not to do any post-processing, if possible, you may create more problems.
    Most likely, your problem is caused by a mistake in the layout.

    The devices are recognized from the layout by LVS...
  18. Closed: Re: Aspect ratio of the matched transistor array

    Even if you have a single transistor, with wide gate, it is recommended to fold its gate to form a multi-finger device, with aspect ratio around 1.

    Interconnects matching is important not only...
  19. [SOLVED]Closed: Re: Can you use StarRC to extract a certain subcell and all its connections to topcel

    No, this is not possible - in StarRC, or in any other industry standard parasitic extraction tool.
    (actually, the goal as you formulated it is not well-defined - what if your net goes to other cells...
  20. Closed: Re: Post layout simulation results differ from prelayout simulation- S21 is negative

    First thing to check is - whether your inductors were extracted as R parasitics, or defined as p-cells or cells that are blackboxed for extraction.
    If it's the former - you have a big problem,...
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    Closed: Re: Extra layers in finfet technologies

    In FinFET technologies, the structure of device (transistors) is much more complex than for planar devices.

    So, in additional to BEOL (Back End Of Line) layers, foundry are using MEOL (Middle End...
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    Closed: Re: Capacitance and fringing equation

    There are many online capacitance calculators, just do a search, for example:

    https://www.emisoftware.com/calculator/coplanar-capacitance/
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    Closed: Re: MOS capacitor when Vgs is -ve

    Usually, accumulation layer formed by holes (in nMOS transistor) is not called a "channel" - a channel is something that allows a current flow between source and drain.

    When AC signal is applied...
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    Closed: Re: ANSYS Totem electromigration check

    Totem, Voltus (or VoltusFi), or any other EM / IR drop analysis tool simulates current flow in R or RC network (for power nets or signal nets).
    When it does dynamic EM / IR simulation, a current...
  25. [SOLVED]Closed: Re: Post layout Monte-carlo simulation with TSMC 180

    Why do you call "nch_mac" a mismatched model?

    From what I know, nch_mac is a macromodel (i.e. a wrapper around a transistor model, that captures some of the parasitics).

    In old nodes, like...
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