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Type: Posts; User: dpaul

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  1. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    1. Get a repo, SVN, Git -- best solution!
    2. Get a filelist or .f file (tracking of files possible but not their contents). More details here -...
  2. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    I am seeing what you have written and it includes none of your project files. So I find it difficult to answer your question.
    What if you remove the file in question from Modelsim project, add it...
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    Closed: Re: Import chipscopes data to matlab

    Sorry, my bad......didn't read #1 thoroughly.
  4. Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    What happens if you use the absolute path inside the RTL?
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    Closed: Re: Import chipscopes data to matlab

    I don't use Matlab!
    So I jst gave the basic idea of using scripts. Now if it can be done in Matlab, good for the OP.
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    Closed: Re: Import chipscopes data to matlab

    Just write a script in your fav scripting language (Bash, Perl, Python) which will read the txt file you have posted and write out the desired file to be read by MAtlab.
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    Closed: Re: Not enough IOB of a certain FPGA

    Hello OP,



    This looks like an internal module design to me. At the peripheral you don't have these many signals.
    If you provide us the project details then perhaps there can be more help.
    ...
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    Closed: Re: Vivado Timing Constraint

    It is Xilinx Design Constraint (.xdc) not "Vivado Timing Constraint ", which constrains the FPGA design as stated above.
    Read the latest version of UG903 for details on XDCs.
  9. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    Make sure the core is regenerated and the new one is used in your project.
    From the IP Sources tab, for the FIFO IP, also verify under Instiantiation Template, that in the generated *.vho file, the...
  10. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    You change the depth & width parameters to get the FIFO size of your choice in Vivado. These options are typically in the 2nd tab, under 'Data Port Parameters' field.

    153532
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    Closed: Re: FPGA ASIC gate count

    Can I know the ASIC gate count of Spartan-6, Artix-7, Kintex-7 and Kintex ultrascale+.

    Gate equivalent is an ASIC terminology and not related to FPGAs. FPGAs are basically composed of LUTs, Flops...
  12. Closed: Re: TC34725 i2c color sensor not working without any error (basys3 vhdl)

    It is in principle a I2C slave. So you take a slave i2c module (your sensor), connect it to a master i2c module (your logic which will acquire the data from the sensor) and put the whole thing in a...
  13. Closed: Re: TC34725 i2c color sensor not working without any error (basys3 vhdl)

    Then you must study, learn more and go to the depth of the problem. Else you will not be able to proceed.

    As ads-ee has mentioned, write a test-bench and verify your design before testing it...
  14. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    For the implementation error problem, read this-

    https://www.xilinx.com/support/answers/41754.html
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    Closed: Re: Circular buffer design

    if ( rd_en = '1' and fifo_empty = '1') then
    data_out <= memory(to_integer(rd_ptr));
    rd_ptr <= rd_ptr - 1;
    end if;


    You want to output data from the memory when...
  16. Closed: Re: Audio file sending via pmod wifi to zybo board

    Yes then go ahead and do it., who is stopping you? :-)


    Then search, read docs, slog, learn.....

    There is already something @ GitHub, there might be other sources also......
  17. Closed: Re: Verilog beginner: is synthetized rtl optimal?

    I think you should be first putting in good quality and verified RTL (there are many trusted sources, Google) and use them.
    Then for playing around and see how the tool is behaving, you can try...
  18. Closed: Re: Verilog beginner: is synthetized rtl optimal?

    First please tell me what is your need, your target.
    Are you trying to <1> write a good RTL or <2> are you trying to test the Yosys tool for a good netlist generation?

    If <1>, you should be...
  19. Closed: Re: Verilog beginner: is synthetized rtl optimal?

    I think you should spend some more time with your Verilog.

    You are assigning the value of a register to an input port?


    Did you try to compile your code before this Yosis stuff?
    It would be...
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    Closed: Re: HDMI in and out , just connected in to out.

    Now that is a separate problem!
    You need to find out yourself to get an HDMI source before proceeding.
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    Closed: Re: HDMI in and out , just connected in to out.

    I would suggest you to first build a successful HDMI pass through project (rather than HDMI I should be saying 480p signal).

    HDMI data in (source can be anything) --> Virtex4 FPGA --> HDMI display...
  22. Closed: Re: Spartan6 (ISE 14.7) how to generate differential clock?

    If there are no more problems then it is time to close the thread! :-)
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    Closed: Re: HDMI in and out , just connected in to out.

    I have to understand what you are exactly doing.

    Is it like the following?


    Raspberry Pi HDMI o/p --> Virtex 4 --> HDMI out to display
    |
    *do something...
  24. Closed: Re: Synth. area reduced when adding a pipeline register

    DC will generate a synth report.
    Have you investigated the DC generated reports in both cases?
    Your answer is likely to be there in the reports.....
  25. Closed: Re: Spartan6 (ISE 14.7) how to generate differential clock?

    An OBUFDS Xilinx primitive might suite your purpose.
    I would suggest you to read the realted "SelectIO Resources" docu for Series6 Xilinx FPGA for details.

    This thread might help :...
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