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    Closed: Re: trannoise result in HSPICE

    What type of circuit and how large is very large?
  2. Closed: Re: How to combine Cadence Encounter Layout and Cadence Virtuoso Layout together?

    Depends a bit, but the most old-fashioned way is to gds-out your encounter file with references to cell libraries (ie. the standard cells) and then in virtuoso import the gds with the libraries to...
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    Closed: Re: Fixed frequency oscillator in verilogA

    ok,

    convergence issues are always a bit tricky to deal with.

    Possibly:

    You could try to soften the transition a bit by introducing rise and fall times.

    Also, how do you define dt?...
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    Closed: Re: DAC Noise Simulation

    Yes, noise depends on the signal, but still can be overlayered by a substantial thermal noise. Assume for example that the DAC is a current-steering one where you terminate the outputs on resistive...
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    Closed: Re: Fixed frequency oscillator in verilogA

    @(initial_step)

    --> initialize the variable next to be equal to

    next T/2 + the start time (the start time is not necessarily 0 based on if you set the tstart parameter for the transient...
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    Closed: Re: Has anybody used Oceane for IC design

    What's oceane?
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    Closed: Re: DAC Noise Simulation

    Well-ish, I expressed it perhaps a bit sloppy, what I meant was that as long as the digital signal is properly generated then it makes sense. Given that you generate a sinusoid through e.g. an...
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    Closed: Re: DAC Noise Simulation

    Assuming that the digital input signal (signal properly generated and conditioned) does not add more quantization noise than the thermal noise NSD at the output, then yes.
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    Closed: Re: Trannoise simulation in HSPICE

    Noise sims typically take time... what Fmax did you try? Normally, the maximum time resolution of the simulator will be dictated by the maximum frequency you want to simulate. And just curious: what...
  10. Closed: Re: Integrated Circuits Filter Resources-Active RC, OTA/GM-C, Switched Capacitor Filt

    What about the low-hanging fruits?

    * https://www.wiley.com/en-us/Analog+Integrated+Circuit+Design%2C+2nd+Edition-p-9780470770108 Analog Integrated Circuit Design, 2nd Edition
    *...
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    Closed: Re: Incisive Intallation using Installscape

    > Do I tell Installscape where DFII installation is already and then install Incisive ?

    No, you can install anywhere you like. The installations are independent (-ish) of each other.

    > Does...
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    Closed: Re: Why lib file only include FF,TT and SS

    What modalities are you comparing?
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    Closed: Re: Smaller die size by tighter SPICE corners?

    Not that many keywords on the top of my head. I am just arguing that if you want to design a transistor with a certain driving strength to meet e.g. setup/hold times for FF corner as well as SS...
  14. Closed: Re: Noise and variability analysis for differential amplifier in cadence

    If you have for example the gpdk from cadence installed, you can quite straight-forward simulate with monte-carlo variations. What's your experience with Cadence? The noise analysis is...
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    Closed: Re: PLL gain and phase margin

    I guess some more information is needed ... do you break the loop when you do the tests and have you designed the phase detector and charge pump such that they are linearized around the stable...
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    Closed: Re: Smaller die size by tighter SPICE corners?

    The more control you have over your process, the more "deterministic" the outcome will be. You wouldn't have to overdesign your circuit to cover all outliers due to the process variations. And would...
  17. Closed: Re: nedding help to setup pole zero analyses in cadence

    Type in the linux shell from which you launch cadence.
  18. Closed: Re: Gnerate spice netlist from Cadence Spectre schematic

    Ah, ok, so then the situation is a bit different, your focus is mainly on the testbench rather than subcircuits.

    From your netlisting experiment in ADE - you tried changing simulator...
  19. Closed: Re: Gnerate spice netlist from Cadence Spectre schematic

    For what purpose do you need to generate it? (Just asking, since you do not get the models).

    * There is export as CDL which is to some extent spice-like and needs some tweaking. From the CIW,...
  20. Closed: Re: Cascoded diode connection for biasing single mirror transsitor

    The feedback loop would help adjust cmfb1 if the cascodes in the cmfb weren't there, but I guess from a DC operating point of view, it helps mimicking the high output impedance current sources in...
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    Closed: Re: 65nm bonding and pad size

    Perhaps stating the obvious now, but the pad size does not necessarily scale with the geometry per se. Pad sizes can definitely be smaller than 100x80 . Are you in control over the bonding process in...
  22. Closed: Re: Problem in layout result of MOS pseudo resistor

    It almost looks too good in the schematic ... what do net8 and net10 look like in the two modalities?
  23. Closed: Re: Probing extracted layout NETs and CURRENTs - How to?

    What tools are you using for simulation and extraction? Dependent on that you have different means of back-annotation to your original schematic/layout and can (or cannot) directly probe in the...
  24. Closed: Re: Unable to plot the waveform while simulation in cadance specctre?

    Sometimes when the simulation is long and you still only look at a limited set of waveforms the amount of data is so low that it is not flushed to disk, but instead kept in memory.

    Sometimes it...
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    Closed: Re: DRC Errors after No Geometry Violations

    It would be good to perhaps point out which errors you see. Are they related to the actual standard cell or the routing?

    Typically, Encounter might not have full support for the following type of...
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