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Type: Posts; User: promach

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  1. Closed: Re: LDO load transient response in the event of a sudden load change

    Why would the AC gain never reach 0dB ?

    Which circuit node introduces the zero near 1MHz ?
  2. Closed: Re: LDO load transient response in the event of a sudden load change

    @ danadakk

    I managed to get the phase margin plot back to normal by using 1.8u instead of 18u for the length of M7, M8, M11 and M17
    However, without output load capacitor CL, AC gain still could...
  3. Closed: Re: LDO load transient response in the event of a sudden load change

    Even with 1us rise time and 1us fall time on Iout, the voltage overshoot and undershoot for Vout is still very serious

    https://i.imgur.com/EeN57Rq.png
  4. Closed: Re: LDO load transient response in the event of a sudden load change

    The following bode plot is without CLoad.

    Note that gain never reaches 0dB ......

    https://i.imgur.com/NukOiv4.png
  5. Closed: Re: LDO load transient response in the event of a sudden load change

    See the following test circuit and simulation result for phase margin:

    https://i.imgur.com/gaO8ChV.png

    https://i.imgur.com/5HU8hsB.png
  6. Closed: LDO load transient response in the event of a sudden load change

    See https://github.com/promach/LDO/tree/development for the LDO circuit.
    Ignore the pictures inside README because they do not reflect the current circuit.

    Without using external capacitor, could...
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    Closed: Re: Trade-off between LDO max Iout AND PSRR

    What do you exactly mean by Rout corner frequency ?
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    Closed: Re: Trade-off between LDO max Iout AND PSRR

    I have two miller compensation. Which one were you referring to ?

    By the way, I changed the feedback path in the PSRR simulation circuit to be AC 0 instead of AC 1
    Then, PSRR is now at 45dB
    ...
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    Closed: Re: Trade-off between LDO max Iout AND PSRR

    What do you exactly mean by "stiffer gate drive" ?
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    Closed: Trade-off between LDO max Iout AND PSRR

    PSRR is inversely proportional to output impedance of LDO.

    But Iout_max of LDO is proportional to width of output mosfet (M20) , Rds of M20 is inversely proportional to width of M20.

    Given that...
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    Closed: Failed coverage in NoC coding

    Why https://github.com/promach/noc/blob/development/spidergon_top.v#L344 failed ?

    always @(posedge clk) cover(data_packet_contains_header[node_num]);

    https://i.imgur.com/cy05Ifd.png
  12. Closed: Re: LDO transient performance enhancement circuit understanding

    The desired Vout is 2.2V
    See Vref, R1 and R2

    Iout = 0 , Vout = 3.2V .........

    Iout = 3A, Vout = 2V


    See 159356
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    Closed: Re: Active Elimination of the RHPZ

    Why Ir is the miller compensation ?
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    Closed: Re: Active Elimination of the RHPZ

    wait, you did not explain with regards to Ir (the reverse current) ?
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    Closed: Questions about microstrip array antenna

    1. Why is 100 ohm transmission line used in this microstrip array antenna ?

    2. Why A quarter-wavelength transformer of 70 ohm is used to match the impedance line of 100 ohm to the impedance line...
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    Closed: Re: Active Elimination of the RHPZ

    1. How Ir helps in miller compensation ?

    2. Why block only If ?

    Note: the screenshots below are taken from the EDN article link in previous post above.

    159280

    159281
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    Closed: Active Elimination of the RHPZ

    How does the following method of Active Elimination of the RHPZ mathematically eliminate RHPZ ?

    159255
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    Closed: Re: AXI arvalid signal issue

    the problem is not about the duration of reset signal, instead it is about how the AXI slave axi_awready signal responds to delayed reset signal

    The assertion of axi_awready as well as axi_arready...
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    Closed: Re: AXI arvalid signal issue

    If I assert reset at t = 0 instead of few clock cycles later, then all pc_status error bits are cleared (no AXI violations).

    Something is still not correct because hardware reset signal is not...
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    Closed: Re: AXI arvalid signal issue

    How is this related to pc_status error bits 32 or 80 ?
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    Closed: Re: AXI arvalid signal issue

    How do I eliminate pc_status error bit 32 in the AXI slave code ?

    159098

    By the way, there is another pc_status error bit 80.
    I have already tried to increase MAXWBURSTS parameter as suggested...
  22. Closed: Re: LDO transient performance enhancement circuit understanding

    I have uploaded the LDO circuit at https://github.com/promach/LDO

    I have few questions :

    1. Why in the second bode plot (which might be problematic PSRR), gain going up near unity-gain...
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    Closed: Re: AXI arvalid signal issue

    This is based on the assumption that AXI master does not need sequential data processing in the case of BRESP returns NACK.

    What if the mentioned AXI master is a CPU or any other sequential...
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    Closed: Re: AXI arvalid signal issue

    Are you suggesting out-of-order transaction where AXI master does not wait for BRESP from AXI slave ?
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    Closed: Re: AXI arvalid signal issue

    However, AWVALID and AWADDR (clocked-reg signal) can only be determined after BRESP and BVALID signal are returned from AXI slave.

    In the case of re-transmitting burst for NACK handling, there is...
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