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Type: Posts; User: Ironlord

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    Closed: Re: How to use a termination resistor?

    Then how do I reduce the overshoot. I am going to work with other drivers and I shouldn't let my FPGA give more than 3.3V or it may reduce the board's life. The peaks are of 4.5-4.7V in average.

    I...
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    Closed: How to use a termination resistor?

    I want to add a termnation resistor to reduce the overshoot of a signal. I configured in Quartus to be 25 Ohm resistance, but it gives me back an error. It says it is not posible to use with...
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    [SOLVED]Closed: Re: Quartus and fixed point

    I have finished compilling it and it works!!!

    I added the fixed_pkg.vhd, fixed_float_types.vhd and txt_util.vhd.
    The sources seemed to be different. I had the file "fixed_pkg_c.vhd" which was...
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    [SOLVED]Closed: Re: Quartus and fixed point

    Ok, I ordered the files from Settings->Files

    Both, "fixed_float_types" and "fixed_pkg_c" are on top. I have tried the two combinations and the result is in both cases the same.
    The error still...
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    [SOLVED]Closed: Re: Quartus and fixed point

    152189
    Hope this help. I think I am doing what you are posting, but it doesn't seem to work.
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    [SOLVED]Closed: Re: Quartus and fixed point

    Could you give me some more details. I have also readen this other answer from you in another thread:
    https://www.edaboard.com/showthread.php?373860-Compile-package-into-quot-ieee_proposed-quot
    I...
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    [SOLVED]Closed: Re: Quartus and fixed point

    Well, I'm using Quartus Lite. I tried to import the library adding the VHD files to the project and referencing them on the place where I use the ufixed data type. It still throwing error with 93 and...
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    [SOLVED]Closed: Quartus and fixed point

    Hello again, guys!

    I am designing a SPWM, which works with a Look-Up Table (LUT) in order to "draw" the sines and a triangular wave.

    Now I want to be able to modify the amplitude of the sine,...
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    Closed: Re: Triangular wave generator in FPGA

    Thanks, that's all I wanted to know. I had another design based on the NCO, but had no idea about how convert the chainsaw into a triangular wave, so I was programming another module in order to do...
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    Closed: Triangular wave generator in FPGA

    I want to implement a triangular wave in an FPGA. Values should go from -2047 to 2047, so I'm using a 12-bit precission.
    The problem is that I want it to be variable in frequency, I want ot be able...
  11. [SOLVED]Closed: Re: Can you help me with this Verilog to VHDL translation?

    It must be something more wrong.
    I added the "if((rising_edge(FPGA_CLK1_50)) then" sentence and changed the reset to "if(reset='1')then, but still not working.

    I don't think I can wrap it because...
  12. [SOLVED]Closed: Re: Can you help me with this Verilog to VHDL translation?

    I agree with that. I am a VHDL coder.
    Anyway, that's an VHDL example I followed in order to generate IRQ interrupts. I achieved to send IRQs from FPGA to HPS and I would like to make more complex...
  13. [SOLVED]Closed: Re: Can you help me with this Verilog to VHDL translation?

    Yes, I forgot this line as I was doing a literal translation, but it is not the only problem.

    About your question...
    There's a lot of documentation written with Verilog examples, so I want to...
  14. [SOLVED]Closed: Re: Can you help me with this Verilog to VHDL translation?

    Both synthesis are correct, but they are not doing the same thing when I program it on the FPGA.
    As I am a newbye at Verilog, probably I messed up with something. Maybe the xor is not correct in...
  15. [SOLVED]Closed: Can you help me with this Verilog to VHDL translation?

    Hello.

    I have this Verilog code which is working, and I would like to translate it to VHDL. I have tried but the VHDL design is not working when I synthetise it, but the VHDL works without...
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    Closed: Re: FPGA to HPS interrupts

    Hello. I'm stuck again, but I guess this time is not FPGA related.
    As I said in my last post, I implemented a module following a tutorial, and now I can see when an interruption is generated. But I...
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    Closed: Re: FPGA to HPS interrupts

    UPDATE: I achieved to generate a interruption, but I had to generate my own VHDL module and insert it in the Platform Designer as a new IP.

    I guess there must be an easier way, so if I solve it...
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    Closed: Re: FPGA to HPS interrupts

    Supposedly, I configured it as ANY and EDGE (instead of LEVEL). So it should send an IRQ0 interrupt throught f2p_irq0 bus every time theres a change in the signal.
    In the kernel module, it seems it...
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    Closed: FPGA to HPS interrupts

    Hello.

    First of all, if this thread doesn't belong to this board, please move it. I didn't know where would it fit better, if here or in microcontrollers.

    As some of you know, I'm working with...
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    Closed: Realtime OS on SoC-FPGA [Xenomai]

    Hello.

    I am working over a Terasic DE10-Nano. It has an Altera Cyclone V SoC which combines FPGA with an ARM-Cortex-A9.
    I have installed the official image, wich is a Linux distribution called...
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    [SOLVED]Closed: Re: HPS-FPGA issues on Intel Cyclone V

    Well, i have been investigating about this topic and finally, by trial and error, I found the answer. I am replying here just in case somebody is in my same situation.

    1st: You must design the...
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    [SOLVED]Closed: HPS-FPGA issues on Intel Cyclone V

    Hello.

    In my learning process I'm trying to work with HPS and FPGA. I am working with a Terasic DE10-Nano.
    I have created a system in the Quartus' "Platform Designer" with the HPS and other...
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    Closed: Re: Correct design to work with MIPI and SPI

    I guess I will proposse this design in order to match the specifications.
    150455
    I have seen the DSIRX and pixel-to-byte IP cores are available. The Decompress/Compress module seems to be the same,...
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    Closed: Re: Correct design to work with MIPI and SPI

    That was also my first thoght.
    But I was told to investigate about it. I was given the scheme I showed you and was told to find a solution for the oposite case.

    I know that I am going from...
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    Closed: Re: Correct design to work with MIPI and SPI

    Hello again.

    150448
    In the image from above, Lattice guys are making a SPI to MIPI converter.
    What we are looking for id for the inverse operation.

    I have found the module MIPI DSI RX, wich...
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