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Type: Posts; User: k_90

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  1. Replies
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    Closed: Re: LVS Subtype error at layout

    Check for marker layers or idenification layers, place both versions of the pcell and look for sub layer differences, ie poly and below
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    882

    Closed: Re: Wellbody layer in tsmc

    If it's not in the design rules I'd look again, try looking for the GDS number or contact the tsmc support./
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    Closed: Symbolic links with in script

    I want to create a symbolic link using a script.

    Within cadence I've saved the wire assistant settings to which I wish to share to the rest of the team.

    I have saved the file in the general...
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    Closed: Re: generate fill dummy metal

    Hello The rules file should have been supplied with the pdk kit, usually the fill program outputs a gds file which can be streamed in and placed on the top level. Be careful using fill scripts...
  5. Closed: Re: minimum width of a metal for handling a given current in CMOS technology

    Example:For a power device I just calculated:

    Minimum metal requirements:
    Metal1-4 Current capacity at 125c is 0.67mA/µ
    Metal5 Current capacity at 125c is 4.02mA/µ

    Total Width = 11,000 um ...
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    Closed: Re: Chip corner stress in IO ring assembly

    You would need to check with the design rules, normally at chip corner there is a keep out area, 0.18 tsmc is 50u for example.
    Metals at the corner edge normally go edge to edge using a 45 degree...
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    905

    Closed: Re: What is 9 metal Track ?????

    It would be the number of layers, the more layer the more complexity and expense!
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    1,870

    Closed: Re: the assura lvs run failed

    yea more info is reqiured. Test the outputs first, make a netlist them stream out, make a gds incase a symbol or pcell is missing or faulty.
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    Closed: Re: game for disabled girl

    Are they easy to program, which language? Would I need external componments? Sorry I don't have much of a clue...
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    Closed: Re: game for disabled girl

    It's the electronic design I'm worried about, i don't know wither to use a microcontroller ( no programming skills) or logic using latches etc .
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    Closed: game for disabled girl

    Hi I've been asked to help design a circuit that would help a severly disabled girl play a simple game.

    The idea is that using two switches* the child could start a game( light and sound) which...
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    [SOLVED] Re: GDS viewer

    Octopus is another one, linux based very fast.
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    7,562

    Closed: Re: off-grid problem

    We have a script that overlaps pieces of path with polygons to avoid by outer edges of the path.

    I may be able to get a copy of it...
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    Closed: Re: Making connections with poly

    As they gates are only 0.56u apart and they are all common in series I would be tempted to connect them together with poly. Jumping up to metal surly would increase the distance between the gates...
  15. Closed: Re: interdigitation

    I ended up doing....

    Z1 = A B A C A G B A D A E B A C A G B A
    Z2 = A B A C A G B A D A G B A C A G B A

    Then you have (with two rows):

    Z1 F Z1
    Z2 X Z2
  16. Closed: Re: interdigitation

    I'd prefer the 8x8 array but I'm not 100% how best to lay it out!
    I also need to slot in another 10 gates somewhere which are not as critical.
  17. Closed: interdigitation

    hi

    I need to layout the following:

    a=32
    b=16
    c=8
    d=4
    e=2
    f=1
  18. Replies
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    3,563

    Closed: Re: When to use Poly routing ?

    I've never heard of that expression "metal leaks more than poly" I think you'll need to clarify what he/she means exactly. All parasitics are creating by the layout designer but can be minimized by...
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    Closed: Re: When to use Poly routing ?

    I'm with fixrouter4400.

    Metal is less resistive so better for routing, thats not to say it could'nt be used back in the old days when we only had poly & metal routing you had no choice....I think...
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    Closed: Re: PROBING and SELECTING NETS in VXL

    If it was me I would firstly probe for the net you need and copy it using the same reference as the destination such as the 0,0 origin.
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    3,729

    Closed: Re: MOS & MOM combination layout

    its a poly poly cap but the principle is the same.
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    3,729

    Closed: site:edaboard.com mom capacitor

    Hi
    I completed a chip a couple of months back with metal over a mos cap using metals 2/3/4 and it worked fine. We didn't have all of the devices to recognise them for lvs but as the capacitances...
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    Closed: Re: Pads Layout

    The size of the pads will be dependant on the process. For 0.35u devices TSMC we use 80x80 pads.

    These are made from an 80x80 metal3/4 plate (esd under) with vias around the perifery. The design...
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    Closed: Re: [50 pts] Help for Passive component Layout

    All of the information you require will be in the design rules supplied to you, set out by the fab. Normally these design rules advise you on the devices available(sp?) ie mim/poly caps resistors....
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    Closed: Re: Higher Level Metal Usage

    Is it connected power? I'd use the M6 if possible if it has a lower sheet resistance, otherwise it wont make any difference, unless you dont need M6?
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