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Type: Posts; User: wizard

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  1. Closed: Re: Is there a way to sort threads by thread starting time?

    Adding "A week ago, newer" constraint in "Find Post:" returns posts in last week, not thread. A thread started last year will be included if it's replied in last week. I am searching for new started...
  2. Closed: Re: Is there a way to sort threads by thread starting time?

    User need to imagine and input some keyword? Sounds unreasonable since there is no keyword targeted.
  3. Closed: Is there a way to sort threads by thread starting time?

    Sometimes I'd like to know what's the recent started threads in a forum. But top threads are most latest replied ones. I searched options in profile. It looks there is no setting to change it this...
  4. Closed: Re: Why not simulate ATPG pattern in ATPG TetraMAX tool

    run_simulation is based on internal fault simulation engine in tetramax. vcs simulation is to simulate the ATPG patterns agaisnt verilog behavioral models. The former has some use models, one of them...
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    Closed: Re: Why we insert Mbist before scan ?

    There is a main reason why MBIST insertion need to be before scan insertion. MBIST logic will be scanned together with function logic to ensure they are defect free.
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    Closed: Re: DFT single chain mode

    I think you mean "lock-up" cell. You only need to look at the test clocks of last FF of the previous chain and the first FF of next chain. If they are same, no insertion; not, insertion. Several tcl...
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    Closed: Re: DFT single chain mode

    If it's not auto supported by tool, why not write a script to do that? This task sound not too complex. Synthesis tools is for manipulating netlist, isn't it?
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    Closed: Re: Huge skew on clock network

    If your clock network is big, large skew is possible. OCV mode is harder to meet. Since your timing has already closed, it is ok.
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    Closed: Re: Why n+ and p+ are used by welltap?

    Sorry, maybe I hadn't made myself understood. I mean why p- substate is not connected to VSS directly, but a p+ implant has to be between them?
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    Closed: Why n+ and p+ are used by welltap?

    Why substrates are not directly connected to VDD/GND? N+ is between n- and VDD. P+ is between p- and GND? Thanks.

    http://en.wikipedia.org/wiki/File:Cmos_impurity_profile.PNG
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    Closed: vhdl code for a memory bist

    Scan test and Memory BIST are not carried out at the same time.
  12. Closed: Re: about wafer probe test

    There are many docs at IEEE.

    Find them by google, boy.
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    Closed: extest train .v

    Maybe the core logic disturbs bsd somewhere. Dump waveform and see why all are X. Dump output from jtag state machine and other critical jtag control signals, so that you can know what the pattern is...
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    Closed: Re: DFT question concerning ATPG

    In most cases, cross domain logic are little. So the coverage loss is little.

    Are you sure X will be captured? I don't think so. I think until you tell the tool that's false path or mutli-cycle...
  15. Closed: Re: Bist low power

    Sorry, I don't have information for them at hand.

    They are popular topics. You can find many stuffs by searching google.

    If you want to go indepth, IEEE papers can help you.
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    Closed: Re: DFT question concerning ATPG

    And these two FFs are in different functional clock domain?
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    Closed: Re: Submodule size in hierarchical flow?

    I agree with you. But my point here is mainly about efficiency. I agree these tools can handle this. But if it takes a week to finish placement flatly, it don't make sense do it in a flat way.

    How...
  18. Closed: Re: ATPG pattern valid ?

    Warnings in ATPG log.

    There might be some warnings during ATPG check. Some kind of circuit can cause mismatch between the values expected by ATPG and simulated by logic simulator.
  19. Closed: Re: Please help me with ATPG using the encounter test

    For TSV-016, most likely, SN/RN is tied during test.



    OK, thanks for your attention, I hope you can help me, the Log says :
    WARNING (TSV-016): CLOCK input pin ... ... , (as I attached above)
    ...
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    Closed: Re: two test clock in ATE test

    Find DFT compiler user guide or RC-DFT user guide.

    There are too many digrams about this.
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    Closed: Re: DFT question concerning ATPG

    You are talking about shift or capture?
  22. Closed: Re: Bist low power

    What's BIST you're talking about here? Memory BIST, Logic BIST?
  23. Closed: Re: ATPG pattern valid ?

    Please have a look at the warnings during DRC check stage.
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    Closed: bsd trst 1149.1

    I think these two flows are equivelant.

    And for the error, it's hard to tell without a real example.

    DC is stupid. It often substitute pad cells for standcell if you haven't set don't touch on...
  25. Closed: Re: DFT with LSSD cells

    You are using DC to do this?

    What is S1? Sorry I don't have time to look up that in manual.

    Because most design are DFF based, I doubt the tool's matrurity on LSSD if you have set...
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