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Type: Posts; User: ranayehya

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    Closed: Embedded Linux Application

    Hello, All
    I am trying to understand some concepts about Embedded Linux and Why engineers use it.
    I read this article

    https://www.eetimes.com/document.asp?doc_id=1277902#

    and I understand...
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    2,540

    Closed: Embedded Linux Applications

    Hello, All
    I am trying to understand some concepts about Embedded Linux and Why engineers use it.
    I read this article

    www.eetimes.com/document.asp?doc_id=1277902

    and I understand that...
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    589

    Closed: Couldn't find design package

    Hello, all!
    I am new in UVM and I have this error while compiling my design



    Could not find the package (design_pkg). Design read will continue, but expect a cascade of errors after this...
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    [SOLVED]Closed: Simulation in questa

    Hello, all!
    I am working on top design module on Questa. The code is like


    module top(
    input wire ..
    output reg ..);
    reg..;
    wire..;
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    [SOLVED]Closed: Re: Instantiating module with inout

    Thanks to you all for commenting. It works when I write it in that way.

    assign sda = enable? sda_reg : 1'bz;
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    [SOLVED]Closed: Re: Instantiating module with inout

    Hello, FvM!
    In the first image, "enable" signal was = 1. So sda = sda_reg and that works
    In the second image, "enable" signal was = 1. sda should = sda_reg but this is not happening
    When "enable"...
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    [SOLVED]Closed: Instantiating module with inout

    Hello!
    I am new in verilog and I begin working on I2C protocol hardware implementation
    The master code works well
    150217
    but when I combine all files together the master code does not work as it...
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    [SOLVED]Closed: Re: Bad handle or reference

    I just solved my issue.
    I should add this line to my initial block in code.sv
    // A = new;
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    [SOLVED]Closed: Bad handle or reference

    I got this fatal in simulation at this line
    A.KeyExpansion(); in TEST.sv file
    TEST.sv file

    import uvm_pkg::*;
    `include "uvm_macros.svh"
    import code_pkg::*;
    module test();
    AES_do A;
    int i;
  10. [SOLVED]Closed: Re: Fatal error while running top module || UVM

    AES_MoniterAFter.sv file's job is to import a C code and predict the output. AES_test is in top module(the interfacing module between UVVM files and verilog code). I already compiled the top module....
  11. [SOLVED]Closed: Re: Fatal error while running top module || UVM

    Yes, I have. Sir, Dave Rich.
    Do you want to see the code ?
  12. [SOLVED]Closed: Fatal error while running top module || UVM

    Hello!
    I am trying to run my first UVM design using these command but I get those errors
    149519
    And the commands(these commands used after compiling the design file and UVM files)


    vlog...
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    [SOLVED]Closed: Re: Segmentation fault in C code

    Hello, Easyrider83!
    This piece of code is a comment. It is my bad that I did not delete it. My apologizes.
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    [SOLVED]Closed: Segmentation fault in C code

    Hello!
    I want to concatenate 2 unsigned char (temp and counter) contain hexadecimal numbers and store them in another variable (after) but this code ives me segmentation fault. Could someone help...
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    Closed: Re: Working with sparten 3e starter board

    I added a schematic file to my project and selected "View HDL Functional Model" option from design menu and it gives me (schematic file name.vhf) file and that is what written inside it and the...
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    Closed: Re: Working with sparten 3e starter board

    When I saw tutorials on YouTube about programming the kit, there was 3 JTAG devices in videos and the kit in the videos was programmed
    This are the switches
    148843
    And this is the LED
    148844
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    Closed: Re: Working with sparten 3e starter board

    148840
    This is what I have done a while ago and I did it again today but the kit did nothing.
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    Closed: Re: Working with sparten 3e starter board

    I edited in constraint file Mr.KlausST and nothing changed.
    NET "z" LOC = "E12" |IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
    NET "x" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
    NET "y" LOC =...
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    Closed: Re: Working with sparten 3e starter board

    Yes, Mr.Barry. I said that
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    1,298

    Closed: Re: Working with sparten 3e starter board

    Sorry Sir. TrickyDicky but I do not get your question very well
    Are all LEDs operate when they get voltage?
    I took an image from datasheet

    148835
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    Closed: Re: Working with sparten 3e starter board

    The constraint file consists of 2 switches and a LED in the board. I switched it on and off and the LED did not work.
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    Closed: Working with sparten 3e starter board

    Hello All!
    I am starting my first project(an and gate) with the kit mentioned above and ISE design suite
    The flow run smoothly. But in the end, the kit did not work although the program succeeded...
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    Closed: Re: Writing a ROM in verilog

    Do you mean that I should put clock and reset?
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    Closed: Re: Writing a ROM in verilog

    Thanks vGoodtimes for your comment but I have another question.
    How to know that my tool will implement my rom as a rom?
    I am using vivado 5.1
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    Closed: Re: Writing a ROM in verilog

    I think it is a 3D array and also I read in tutorials on verilog that initial block does not use in verilog
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