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Type: Posts; User: Tieny

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  1. Closed: Re: How to find the operating frequency for an ASIC?

    The frequency is depend on process, design margin ,.. If your FPGA board signoff @20Mhz , there are no reason you increase @30Mhz if you dont want to face with setup timing violation ,..

    Tiep Ngo
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    Closed: Re: DFT Visualizer Data View

    It means your FF.Q expected value 0 after unload (shift out the data to the scan chain) .
    I can explain more about it :
    Q 000 - 100 - 000
    [shift in ] - [capture ] -...
  3. Closed: Re: Tool inserted DFT lockup latch is not transparent in functional mode (no test por

    Hi ,

    The lockup latch only active in scan shift path (FF1.Q -> LU.D -> FF2.SI ).
    So dont care about it on functional mode.

    Tiep Ngo
  4. Closed: Re: Running Deep Learning Based Plant Diseases Recognition

    Thanks, never try that but it's a good idea

    Tiep Ngo
  5. Closed: Re: Running Deep Learning Based Plant Diseases Recognition

    That's right, it just a dataset , you need a framework for Machine Learning like lite tensorflow on the Pi but the learning time will slowd due to CPU core and dont have GPU support.

    Tiep Ngo
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    Closed: Re: Suggestions of RTOS for STM32F429

    I'm using OpenRTOS for my Discovery F4 kit . No issue till now.

    Tiep Ngo
  7. Closed: Re: DFT parallel pattern simulation mismatch analysis

    For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure.
    What you should trace back is the clock , time it lanuch in...
  8. Closed: Re: For DFT perspective ,what happens when there are no capture clock

    1. If your design is HATPG you can check OCC ( On-chip Clock Control ) for more info. DFT will create 1 scan_clock for this purpose.
    2. If your design is not HATPG, it meant you have 3 clock domains...
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    Closed: Re: What is meant by Split CODEC IN DFT ?

    Can you point full statement in your document ?

    Tiep Ngo
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    Closed: Re: LBIST low test coverage

    LBIST coverage is a tradeoff : if you want more cov , you need more logic --> more area, power, testtime ,...

    Tiep Ngo
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    Closed: Re: MBIST DONE & GO failing conditions

    1. DONE signal : Test time not enough. GO bit will not compare.
    2. GO/GO_ID signal :Should the failure on the controller / mem_inf.

    Tiep Ngo
  12. [SOLVED]Closed: Re: Post place & route netlist simulation is failing although STA is ok

    Some item you need to check :
    1. Clock period ? Is it correct with your SDF .
    2. Simulator option is correct with your SDF ? -mindelay with min conner and -maxdelay with max conner ? Using notiming...
  13. Closed: Re: For DFT perspective ,what happens when there are no capture clock

    First , I will cause the error when you are doing insertion (C1 violation) and stop your flow !
    Second , if your flop cannot capture clock , how can it operate in functional mode ?
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    Closed: Re: Multiple scan clocks

    1. How to decide scan clock out of 4 clocks ?
    -> We also have OCC only choose 1 clock ( scan clock ) from the TOP level.
    2. I have read somewhere that only one clock needs to be active , Why...
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    Closed: Re: scan chain inside memory

    That's correct, in my experiment we also have ram sequential pattern to cover all logic from FLOP to D pin of memory.
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    Closed: Re: Dynamic IR drop analysis

    As DFT role, better pattern distribution for HATPG and MBIST controllers .
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    Closed: Re: fifo with ram or flops

    Thanks for the table. On some design, I faced it used some small srams for the fifo from the output of Serdes , still wonder why .
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    Closed: Re: DFT interview questions

    All about SCAN, how's about MBIST, LBIST or BSCAN ?
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    Closed: Re: How do you reduce Atpg Abort faults?

    It depend on your pattern type : SA, TR, Ram seq , ..
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    Closed: Re: Questions on DFT autofix

    1. at RTL
    2. the selection of mux will be scan_mode so when you do formality check with functional mode it should be fine.

    Autofix is stupid tool so dont abuse it .
    Regards
  21. Closed: Re: Why higherk frequency circuit may encounter hold time violation for low frequency

    Example we have some delay variable : FF0 (pos-edge ) -> FF1 (neg-edge) , T = peirod of CK
    T_launch : CK -> FF0/CLK
    T_comp : FF0/Q -> FF1/D
    T_cap : CK -> FF1/CLK

    Hold time check requirement :...
  22. Closed: Re: Why higherk frequency circuit may encounter hold time violation for low frequency

    It could be effect if crossing clock domain.

    - - - Updated - - -



    Sorry, my mistake . It could be encountered with half cycle.
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    Closed: Re: Prime time tool of Synopsys

    What kind of input file ?

    Generally , you need lib (db,lib) ,netlist file, sdc file .
    If you alread have session , you can restore it .
  24. Closed: Re: SDF back annotation after synthesis fails: No timing checks annotated

    if you use VCS as simulator, report_timing in UCLI mode will help
  25. Closed: Re: How to stitch multi bit flip-flop into wrapper chains in tessent -shell

    tessent analyzes wrapper cell base on IO ( in/out) itself.
    It would be helped if we have more information
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