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    Closed: Re: how to generate 4MHz clock from 2 MHz clock.

    See how 2 MHz clock is derived from DDS MSB phase[31]. You can generate 4 MHz in a similar way by utilizing phase[30] too.
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    Closed: Re: Overvoltage Protection

    Look again, the circuit is fine.

    If you don't have one of those "digital transistors" with built-in base resistors, you need to add an external base resistor.
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    Closed: Re: how to generate 4MHz clock from 2 MHz clock.

    The xapp868 design is a digital PLL that can easily generate 4 MHz along with the 2 MHz output.
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    Closed: Re: Phase detector with synchronous logic (FPGA)

    I don't agree. You get a much higher phase resolution by I/Q demodulation, only limited by the ADC resolution and signal noise.
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    Closed: Re: Input LC filter inductor is being shorted out

    The filter has still a fair attenuation at the 700 kHz fundamental. If you want stronger high frequency filter effect, you can go for other topologies like L-C||RC, or 2-stage. I guess, you didn't...
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    Closed: Re: Phase detector with synchronous logic (FPGA)

    I agree that processor is simpler. Additional logic (e.g. FPGA) is however needed due to the high sample rate, unless you have a fast signal processor that can stream in samples at 40 MHz. In this...
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    Closed: Re: Phase detector with synchronous logic (FPGA)

    A possible solution could be to determine the analysis frequency based on the zero crossings and then multiply the acquired signal with sine and cosine reference functions of this frequency.

    MAX10...
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    Closed: Re: Bias current sensor for floating earth

    U2 LED reversed, but I see what you mean.


    You should know. If circuit isolation is a safety feature, your present design may also conflict with essential standards, e.g. IEC 61010 or other other...
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    Closed: Re: Phase detector with synchronous logic (FPGA)

    The 50 us limitation wasn't mentioned yet. In this case, "processing the entire dataset" is in fact more promising. Question is if you know the exact frequency beforehand or need to extract it from...
  10. Closed: Re: 14 bit adc output to 5 bit data conversion in VHDL

    May be the question is that trivial, may be some specific coding is intended. The OP missed to ask a clear question.
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    Closed: Re: Phase detector with synchronous logic (FPGA)

    The multiply idea sketched in post #1 is basically good, but it should be extended to I/Q demodulation to work over 0 to 360 degree. You can either generate a 90° delayed copy of one input signal,...
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    Closed: Re: transfer function of sc amplifier

    May be mathematically correct, but wrong in Z transform context.
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    Closed: Re: Bias current sensor for floating earth

    Don't think so. U1 LED is driven with wrong polarity and has negative transistor supply.

    157827

    Many previously mentioned problems are still present, ignoring balanced ground fault, huge...
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    Closed: Re: how to generate 4MHz clock from 2 MHz clock.

    A bit more complex. You'll design a kind of software PLL with 2 and 4 MHz output, locked to the 2 MHz reference. Dynamic phase shift might be used if the phase jitter requirements are very strict....
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    Closed: Re: Non-Invasive High Voltage Coupling?

    High Voltage Coupling means what, exactly? Measuring current, voltage, linearly, which range? HCPL-0370 reference suggest you want to compare current magnitude with a threshold, if so, what's the...
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    Closed: Re: 72 pin SIMM pinout and circuit

    If you experience contradicting hearsay specs, why not refer to major manufacturers datasheets instead?
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    Closed: Re: how to boost microvolts to higher voltages?

    I believe, you either don't read the answers or don't understand it. I have no other explanation for seeing the circuit in post #45 that has been already recognized as non-working. If you want to...
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    Closed: Re: Impedance calculation in CMOS circuit

    Incomplete problem description results in ambiguous or useless answer. At least one unclear point is floating substrate nodes.

    Transconductance is a small signal quantity, respectively it's valid...
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    Closed: Re: transfer function of sc amplifier

    1/2 sample period is no meaningful quantity in sampled data system. Output is only observed at integer multiples of sampling period. You'll see if you cascade two of the shown stages. What's the...
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    Closed: Re: Bias current sensor for floating earth

    A symmetrical fault example, referring to your previous design. How would you detect it?

    157803

    - - - Updated - - -


    The file is different from posted schematic (incomplete). The new scheme...
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    Closed: Re: how to boost microvolts to higher voltages?

    I feel that some points should be sorted out.

    You have been originally asking how to amplify ĩV signal to mV, with minimal supply voltage.
    Later you switched to 1.45 V input voltage and 8V...
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    Closed: Re: Bias current sensor for floating earth

    The idea of an ungrounded network (IT network) is to avoid short circuit currents in case of a single ground fault while being able to detect the fault.

    The 10 k resistors in your circuit cause a...
  23. Closed: Re: RHP poles always appear in my designed amplifier

    A RHP pole in the open loop transfer function can be only generated if the feedforward turns into positive feedback, likely to happen for the post #1 circuit.

    How do you measure the transfer...
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    Closed: Re: Bias current sensor for floating earth

    Your monitor circuit is generating huge leakage currents and power dissipation and surely no acceptable IMD solution.

    What is your of insulation resistance threshold specification?

    - - -...
  25. Closed: Re: Waveform saving upon trigger in windows from Oscilloscope

    MSO2000B series has 1M data points memory, about 10 sec @ 100 kSPS. Timebase can be set up to 100 s/div, 1000 s total length with respective lower time resolution. Not sure if quasi continuous data...
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