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Type: Posts; User: abonic

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  1. Replies
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    Closed: Re: On Settling of a fully-differential amplifier

    Thank you erikl, it is really a good news for me. I'll leave this problem alone, and go to tapeout.
    when the testing results come out, I'll post some results.
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    Closed: On Settling of a fully-differential amplifier

    Dear guys,
    Due to the periodic drift of the output CM level, the outputs (Voutp & Voutn) of a fully differential amplifier accordingly drift even with sufficient SR and UGB, as shown in the...
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    Closed: Re: The advantages of Snake-Shape MOS Transistor

    Pcell does not have gate contact typically, you have to add it in your layout:)

    - - - Updated - - -



    Pretty reasonable
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    Closed: Re: The advantages of Snake-Shape MOS Transistor

    dear dick,
    I have no idea of what the "gate" between the serpentine folds actually is.
    It seems this structure only increases the parasitic MOS/Cap just as ajay said.
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    Closed: Re: The advantages of Snake-Shape MOS Transistor

    Quite like;-)
    Actually it is a N-Ch MOSFET
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    Closed: The advantages of Snake-Shape MOS Transistor

    Dear all,
    Recently, I've found a type of MOS Transistor characterized by snake-shape layout (pls refer to the figure attached),
    121457
    NMOS

    one prominent advantage of this type of...
  7. [SOLVED]Closed: Re: Ground Splitting Issue of Mixed-Signal Layout

    Dear erikl,
    You've explained this issue throughly and quite comprehensible.

    Thanks a lot!
  8. [SOLVED]Closed: Re: Ground Splitting Issue of Mixed-Signal Layout

    Dear erikl,
    According to you suggestion, AVSS & DVSS are finally shorted at the top level. However, it is not what I expected.
    AVSS & DVSS are typically separated at the PAD Ring, thus the PAD Ring...
  9. [SOLVED]Closed: Ground Splitting Issue of Mixed-Signal Layout

    Dear all,
    I'm doing the layout for a mixed-signal system on the P-SUB CMOS Process these days, there're two grounds AVSS & DVSS for Analog domain and Digital Domian.
    Both Analog Core and...
  10. Closed: Re: How to do a simultaneous selection in Virtuoso Layout

    Not the reason.
    I suppose it is due to some facts which are out of our normal scope of view.

    PS: These days it is again out of work:)
    What a weird problem!
  11. Closed: Re: How to do a simultaneous selection in Virtuoso Layout

    It is amazing when I find the "shift+select" function has been recovered automatically.
    It is really weird.

    Many Thanks to electronics_rama & vijaya.kumar for your suggestions.

    Still open for...
  12. Closed: Re: How to do a simultaneous selection in Virtuoso Layout

    Neither Can it work:sad:
  13. Closed: Re: How to do a simultaneous selection in Virtuoso Layout

    It is due to the fact that "shift+select" method cannot work as expected that I seek help:roll:
  14. Closed: How to do a simultaneous selection in Virtuoso Layout

    Dear all,

    Recently, I've found that I cannot do a simultaneous selection in Virtuoso Layout.
    For example,
    120141

    I cannot select the two metal traces (A & B) at the same time.
    I'm highly...
  15. Closed: Low Power Design for Pseudo-Random number generator Using LFSR

    Hi Guys.
    Recently, I'm getting interested in the PRN Generator Using Linear Feedback Shifting Register(LFSR).
    If Low Power Performance is desired, which Logic Type and clock strategy are...
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    Closed: Re: On DNL/INL with reduced bits

    It only a theoretical discussion, not a real case.:-P
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    Closed: On Noise for MOSFET work in linear region

    Hi guys,
    for noise calculation, we are quite familiar with MOSFET work in saturation region, the channel noise current is widely recoginized as \bar{I_{n}^2 }=4KT\gamma gm. What if it works in...
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    Closed: Re: On DNL/INL with reduced bits

    Yeah, I understand what you mean in your case.
    Let's now think about a bad case, where an 10-bit ADC has 16-LSB maximum DNL and 32-LSB maximun INL. What if we only use the MSB 9-bit to calculate...
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    Closed: On DNL/INL with reduced bits

    Hi, guys
    If I only use the MSB K bits of a nominal N bits ADC (N>K), what's the relationship between the MSB K bits DNL/INL and N bits DNL/INL.

    To give the question more apprehensible, assume the...
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    Closed: Re: A DNL Testing Problem, why could it happen

    Dear dick & dominik, the method provided by dick is pretty practical. In addtion, the packaged data from the raw ADC output was contaminated by an unexpected logic error during the packaging process....
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    Closed: Re: A DNL Testing Problem, why could it happen

    Dear dick & dominik, your suggestions are well inspiring. It is the board issues that deserve an overhaul. I'll do it later and post the results. Thank you.
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    Closed: Re: A DNL Testing Problem, why could it happen

    Dear FvM,
    I'v Checked the code, and there is nothing wrong with it. Actually, it is a universial code that is applied in many of our applications.
    Could there be any else reason...
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    Closed: A DNL Testing Problem, why could it happen

    Hi gays,
    I'm now testig the DNL of AD976A (a 100KSps SAR ADC) using the standard sinusoidal code density method. It turns out that too much counts appear near the zero-crossing point(4096th bin) in...
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