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Type: Posts; User: dick_freebird

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  1. Closed: Re: Negative power supply delay in bias sequencing circuit

    Appears that both supplies have an externally asserted,
    hard turnoff (maybe the battery-drop, but maybe some
    other "feature" of the power supply controller(s).

    A question right off the top is,...
  2. Closed: Re: Spikes in output voltage in Buck Converter

    Additionally the probe "loop area" (between tip+shaft,
    and ground clip) is an inductive pickup for all the
    inductor leakage field, and your choice of ground-
    point embeds more or less I*R,...
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    Closed: Re: Designing of high GBW opamp

    You speak of reducing "the" channel length, but this is not
    something you should treat as a "single setting". Different
    functions may likely want different geometries.

    For a load you might...
  4. Closed: Re: Reducing leakage by applying negative Vgs (NMOS)

    You want real device measurements, calculations are only
    as good as the data, assumption, simplifications behind
    them.

    I've been inside foundry and I've been fabless and the only
    thing that...
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    Closed: Re: Semiconductor software simulation

    I do not know, I recall "seeing it go past" as I was looking
    for open source circuit simulation tools. I'd look for free
    versions of PISCES, SUPREM, ATLAS, ATHENA - I think
    it was one of those...
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    Closed: Re: How to make a coil to be resonance?

    Every coil has a SRF (self resonant frequency) but you
    may not like where it is. Usually people try to stay below
    SRF when they care about inductance as a value.

    A low frequency self resonant...
  7. Closed: Re: Reducing leakage by applying negative Vgs (NMOS)

    This works, to a point. However, there is a phenomenon
    known as GIDL (gate induced drain leakage) which will
    eventually cause the leakage floor to rise back up from
    its minimum, as you further...
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    Closed: Re: Semiconductor software simulation

    Generally referred to as TCAD, different tools will either
    create a finite element mesh of doping and oxide features
    from a process flow deck, or perform device electrical
    simulations based on...
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    Closed: Re: Latchup Caused by diodes

    NMOS and PMOS are your explicit, desired devices. Each
    has parasitic BJT "baggage". Thie baggage forms numerous
    SCR structures throughout the chip and each one needs
    to have a wide enough base...
  10. [SOLVED]Closed: Re: Lenovo laptop problem during installing LINUX OS

    Some distros are much more helpful / forgiving than others.
    Ubuntu worked out pretty well for me, on a Dell which has
    a near-orphan GPU. Red Hat / CentOS, I could never get
    the display right...
  11. [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    It's unlikely your LDO will respond to the digital switching
    transients (orders of magnitude slower control loop. than
    technology edge-rates). You will depend on some filter
    bank to "soak up"...
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    Closed: Re: Leakge current in low Vt cells

    Because the subthreshold slope has not intersected the
    junction leakage floor by the time you hit Vgs=0.

    This not only makes the leakage higher, it makes it highly
    variable - a nominal...
  13. Closed: Re: ASIC Physical Design

    Yes.

    Your noise margin (for a fully settled output) is the
    distance from rail voltage to threshold voltage. At rails
    come together (I*R applies to both vdd and vss) the
    distance must shrink....
  14. Closed: Re: 2.4GHz WiFi module causing interference on 433MHz RF receiver module

    None of those regulators have any PSRR left at the fundamental
    so I wouldn't rule out conducted emissions / susceptibility as
    potential actors. Maybe a RF choke between regulators and
    each of...
  15. Closed: Re: 60dB attenuator prior to spectrum analyzer, how to?

    Are you really after the experience of building, or do you
    just have a measurement job to do?

    I have an assortment of SMA "bullet" attenuators, of course
    these are lesser (3dB, 6db) but you...
  16. Closed: Re: Why BJT is used for voltage reference and not CMOS

    A couple of other reasons:

    PN forward voltage (once you're up out of the leakage /
    recombination floor) is very well controlled and varies not
    much. PN forward voltage is log-linear across a...
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    Closed: Re: High Speed Data level converter

    Depending on how sensitive you are to things like power
    and timing symmetry and channel count, this could be a
    single "logic level" PMOSFET and a resistor load to -5V.
    But hogs power half the...
  18. Closed: Re: In snapback mechanism how voltage reduces when parasitic NPN is turned ON?

    The voltage reducing, is an outcome of testing it with a
    current source. If you tested with voltage you'd see
    current "snap up" instead (and probably fry the sample
    before compliance limit kicks...
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    Closed: Re: Ambiguous result with Analog I/O

    That pad probably has some baked-in design constraints
    as it's meant to be a power pad - might include clamps,
    decoupling and the output is supposed to be the same
    as the input only when applied...
  20. Closed: Re: Opamp buffer with 400nF output capacitance going unstable?

    I would not expect any op amp to be very happy about
    that kind of load. You have a dual problem, the voltage
    regulation (esp. load rejection) wants no resistance but
    the stability wants a zero to...
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    Closed: Re: Design of LNA using CMOS transistor

    In fact there is no "CMOS transistor" - there are NMOS and PMOS.
    As a rule "RF guys" appear to prefer the zero-VT device for gm
    and IDsat, relative to capacitances.

    You can find canned...
  22. Closed: Re: output changes when I touch the enclosure

    I would guess that in an industrial environment, with an
    ungrounded or poorly grounded (i.e. "earthed") case, you
    are adding 50/60Hz hum to the local "ground" and some
    rectification / charge...
  23. Closed: Re: Finding duplicate reference designators in Design Entry HDL Schematic

    DRC is layout design rules check.

    SRC is schematic rules check (may also be called ERC,
    electrical rules check).

    Maybe your tool does not care.

    Maybe your tool offers some "auto-renumber"...
  24. Closed: Re: How to achieve Vref changing with Vdd

    If you're talking about a bang-bang, switched current source
    triangle wave (or sawtooth) oscillator, I have had best luck
    with (1/3) / (2/3) resistor dividers as low and high "references"
    (like...
  25. Closed: Re: How to achieve Vref changing with Vdd

    Usually "reference" means an invariant quantity, not
    "tracking".

    You can build in relationships by how you propertize
    the sources, or use vcvs or even resistor dividers
    depending on how the...
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