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  1. Replies
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    Closed: Re: UNKNOWN BYPASS problem

    thanks for comment. I have used a 4.7 k ohm resistor for pulling up HSWAPEN pin. now I changed it with a 330 ohm resistor and all of them are 0 volt.

    - - - Updated - - -

    in ug380 it is written...
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    Closed: Re: UNKNOWN BYPASS problem

    I have a development board with the same FPGA that works properly. when I do "initialize chain" in my development board and my custom board, I see the exactly the same signals.
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    Closed: Re: UNKNOWN BYPASS problem

    yes I have checked it. I have taken photo of them.
    TDI:
    155774
    TDO:
    155775

    155776
    TCK:
    155777
    TMS:
  4. Replies
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    Closed: Re: UNKNOWN BYPASS problem

    Hi KlausST
    thanks for the reply. I have checked it multiple times. I have measured them when I initialize the chain. they are constantly 3.3 and 1.2 volt.
    I have used a very high quality PMIC in...
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    Closed: Re: UNKNOWN BYPASS problem

    thanks berry for attention. you are right. this is my schematic:
    155764
    155765
    I have checked the jtag signals on FPGA pins. they are electrically connected. I expect the IO pins be 0 or 3.3 volt....
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    Closed: UNKNOWN BYPASS problem

    hey guys
    I have designed a custom board with a fpga. when I do initialize chain in iMPACT I recevice this message:

    I have measured the voltage of all vcc pins. they are correct. but some IO pins...
  7. [SOLVED]Closed: Re: problem with programming the xilinx fpga

    Thanks barry for your reply. I found the problem. the problem was the program pin of FPGA was not pulled up.
  8. [SOLVED]Closed: Re: problem with programming the xilinx fpga

    thanks for your attention. no i don't have.
  9. [SOLVED]Closed: problem with programming the xilinx fpga

    Hey guys
    I have used XC6SLX9-3TQG144I in my design. according to data sheet the jtag circuit must be like the illustrated image. I have implemented it in my board.
    155174
    my problem is that when...
  10. Closed: Re: Want help to purchase a development board

    I recommend you to buy a RPi board. there are many reference books and tutorial on Internet. It is also very cheep.
  11. Closed: How to config GPMC on beaglebone black?

    hey guys
    I am beginner in embedded linux. I want to send some data to a FPGA with GPMC port of a beaglebone black board. I'm using kernel version "Linux beaglebone 4.14.79-ti-r84 #1 SMP PREEMPT Tue...
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    [SOLVED]Closed: Re: FSK demodulation poblem.

    thank you. You helped me very much. I have no idea how I can thank you.:clap:
    you're right. I modified it and it according what you said and now it works very well.
    I want to ask you another...
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    [SOLVED]Closed: Re: FSK demodulation poblem.

    thanks for your attention and your help.
    I think calculated the sum in this block diagram:
    142777
    142778
    and I have illustrated my signals in this image:
    142779

    in the above image F1 =...
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    [SOLVED]Closed: Re: FSK demodulation poblem.

    thanks for the comment. this is my algorithm:
    142709

    I have simulated it in MATLAB/simulink environment.
  15. Replies
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    [SOLVED]Closed: FSK demodulation poblem.

    I want to simulate the FSK demodulator. these are my parameters:
    F1 = 16.5 kHz - 64 Hz, F2 = 16.5 kHz + 64 Hz.
    as the difference between F1 and F2 is very small, I can't extract my data correctly....
  16. Closed: Re: How to implement FSK modulator/demodulator on FPGA?

    if I calculate its fft, I will find out there are f1 and f2 frequencies in my waveform but I don't where the frequency is f1 .
  17. Closed: How to implement FSK modulator/demodulator on FPGA?

    Hello guys
    I want to implement FSK (frequency shift keying) modulator/demodulator on FPGA. I have no idea how I can do it. could you please guide me?
    thanks a lot.
  18. Closed: Re: how to reduce jitter from a video stream?

    thanks for your attention, you have always helped me. I don't know how to thank you.
    I tried those points but nothing changed.
    the timing fails in the FIFO. the source and the destination of the...
  19. Closed: Re: how to reduce jitter from a video stream?

    thanks for the comment. those chipscopes show the same data. the data and trigger are the same. in the below Image I have shown the timing report.
    139103
    there are two timing problem, but they are...
  20. Closed: Re: how to reduce jitter from a video stream?

    I'm sure that the clk140 is a 75MHz clock.
  21. Closed: Re: how to reduce jitter from a video stream?

    thanks for the reply.
    these are my synthesis and implementation option:
    139006
    and
    139007
    and
    139008
    and
    139009
  22. Closed: Re: how to reduce jitter from a video stream?

    Thanks for the comnent. I am sure that chipscope is showing wrong data, because when I remove some parts of my design, it shows valid data. I am totally confused.

    - - - Updated - - -

    Could you...
  23. Closed: Re: how to reduce jitter from a video stream?

    - - - Updated - - -



    thanks for the comment. I am sure that I have not used any signal from one clock domain in another clock domain. I have put a fifo between two clock domain. I don't know...
  24. Closed: Re: how to reduce jitter from a video stream?

    thanks for the comment. I will consider them. I don't know why chipscope does not work for me, for example I have used a counter to count the number of writes or reads from memory, but when I am...
  25. Closed: how to reduce jitter from a video stream?

    Hi guys
    I am working on a project with fpga (spartan 6 xc6slx9 tqg144). my input is parallel video stream. it consist of 8 bits data and a 27 MHz clock signal. I want to store 4 frames of video and...
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