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Type: Posts; User: matrixofdynamism

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  1. Closed: Re: VHDL: How to create type for unconstrained array for entity port

    Yes, but where to declare the type? In a package? If I declare it in a package then how to make the generic called word_len to reach the package so the inner dimension of the p_in_t can be...
  2. Closed: VHDL: How to create type for unconstrained array for entity port

    Here is the entity:


    entity col_piso_sr is
    generic (
    word_len: natural := 8
    );
    port (
    p_in_7: in std_logic_vector(word_len-1 downto 0);
    p_in_6: in std_logic_vector(word_len-1...
  3. Closed: Re: Can one force ModelSim to flag signals with multiple drivers?

    Its just that the synthesis tool from Altera (now Intel) takes so much longer than ModelSim to do its job
  4. Closed: Re: Can one force ModelSim to flag signals missing signals in sensitivity list?

    These answers are helpful. I learnt that the process to generate next state is combinatorial and thus should have its own process. It is a "good practice".
  5. Closed: Can one force ModelSim to flag signals with multiple drivers?

    Signals that have multiple drivers (by mistake of course) may look fine in simulation sometimes and become X at other times. When one tries to synthesize the code, it will always be flagged up as...
  6. Closed: Is there special way to map address to SDR SDRAM?

    SDR SDRAM like other DRAMs contains banks, rows, columns. Thus, to get maximum efficiency, I assume that there would be some non-trivial way to translate memory address to bank, row and column...
  7. Closed: Re: What determines the number of rows in an SDRAM?

    So it is an arbitrary choice of the SDRAM designers? I see.
  8. Closed: What determines the number of rows in an SDRAM?

    SDRAM is divided into banks, each bank into rows and each row into columns. What determines how many rows will be there in an SDRAM?
    Is there a formula used to go from a single memory location...
  9. Closed: Can one force ModelSim to flag signals missing signals in sensitivity list?

    In VHDL we often use processes not trigerred by clock e.g next state process for FSM. In this case, there may be a long list of signals that must be put into the sensitivity list.

    I have noticed...
  10. Closed: What is difference between row and page in SDRAM?

    An SDRAM consists of multiple banks, we have to "open" one row in bank at a time for reading and writing and then "close" it by doing precharge. I am trying to understand how it all comes together...
  11. Closed: What to do if Nios II program does not fit into on-chip memory?

    Tutorials teach that we use on-chip memory to store the Nios II application program. However, what to do if we do not have enough space on it? What off chip options do we have?
  12. Closed: How to find direction of signal travel in a given circuit?

    I am analysing signals used by a game console to communicate with a controller. I want to find out which signals are unidirectional and which way they communicate and which signals are bidirectional...
  13. Closed: What does it mean to pipeline a multiplexer, how is it done?

    For very large multiplexers in FPGAs, there will be a huge propagation delay that may create a critical path and cause timing violation.

    Therefore, one possibility I assume is to use multicycle...
  14. Closed: Re: Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    I have not used BFM yet since I thougt that SystemVerilog is required as they are written in SystemVerilog and I have no idea how they can be used from VHDL testbench.

    Anyway, is it also not...
  15. Closed: Re: What is the purpose of the Avalon-MM master and Avalon-MM slave templates?

    OK, while I understand the purpose of the Avalon-MM slave, what about the master template? Won't the master always be a Nios II? Then why do we need this Avalon-MM master template?
  16. Closed: Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    The BFMs are used to help with verification of Qsys components being written by the developer. Is this true?

    If so, then must one know SystemVerilog to use them? Do they fully support VHDL?
  17. Closed: What is the purpose of the Avalon-MM master and Avalon-MM slave templates?

    The Intel website has these:
    https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html...
  18. Closed: Do functions and procedures infer registers in VHDL?

    Functions and procedures are used to define often repeated sequence of instructions on data into a single place like in any other language. Is it true that in VHDL they are only able to infer...
  19. Closed: What is the max data rate at which this opto-isolator can used?

    The LITE-ON LTV-817 is a High Density Mounting Type Photocoupler. Its datasheet can be found here. I have found that datasheets of many opto-couplers do give the data rate. However, this one doe not....
  20. Closed: Re: Acquire data out from a PC using MATLAB

    We need more information on what you are trying to do
  21. Closed: Connecting FPGA board to an external device for IO, what precautions to take?

    I am going to connect my FPGA board to my PlayStation controller port. The FPGA shall monitor the data going back and forth between the console and the controller. The basic concept on how to get the...
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    2,312

    Closed: Re: use C to program FPGA

    I have heard about OpenCL being used to describe a digital circuit at a very high level of abstraction, almost like a high level programming language. However, when using tools that do something like...
  23. Replies
    13
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    1,195

    Closed: Re: Implementing Look up table in FPGA

    Please remember that in case you want to have sinusoidal values and don't have enough logic resources for the whole look up table, an alternate is to use CORDIC. It is a very neat algorithm.
  24. Closed: What methods exist for division in FPGA

    What methods exist for division (fixed point) in FPGA and what are the advantages and disadvantages of each?
  25. Closed: Create test vectors from real world signals

    What is the simplest way to record signals using an oscilloscope or logic analyzer and then use them to create test vectors for a VHDL/Verilog design?
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