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Type: Posts; User: erikl

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  1. Replies
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    Closed: Re: Self cascoded differential pair transistors

    Hi Junus,

    yes, I know his book and several papers by Johan Huijsing, very instructive ones, and I remember I've successfully used his class-AB output stage with its complementary floating current...
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    Closed: Re: Self cascoded differential pair transistors

    Thanks a lot, Junus, for your summary. But you can be sure that I always read the whole thread before I answer. :smile:

    Re. self cascoding I've seen similar results like you reported, then decided...
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    Closed: Re: Self cascoded differential pair transistors

    Maybe it's a (somewhat obscure) abbreviation for self-biasing cascoded transistor. The upper transistor(s) need their own p-in-nwell substrates, which they bias themselves.
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    Closed: Re: Maximum current of the CMFB circuit

    Right: the 2nd circuit can adjust the common mode level faster than the 1st circuit by delivering more current to its output stage and its capacitive load.
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    Closed: Re: Maximum current of the CMFB circuit

    Yes, I'd think so, even if you perhaps wouldn't need the higher gain: the common mode gain of the diff amp is (should be) rather low, in the order of 1, so a low CMFB (differential) gain in the order...
  6. Closed: Re: CMFB biasing current in fully differential Opamp with adaptive current source

    Very true. But what if the common-mode voltage is just - say - on its half way to its optimum level, before a real large signal arrives at the output stage?

    Yeah, that's what I meant.
  7. Closed: Re: CMFB biasing current in fully differential Opamp with adaptive current source

    As you probably know, a differential output stage absolutely needs a CMFB, because otherwise the output levels would be undefined.

    So CMFB's mission is to keep the voltage levels of the...
  8. Closed: Re: CMFB biasing current in fully differential Opamp with adaptive current source

    I'd think so, if you want your diff amp react to large signal/step input fast enough.
  9. Closed: Re: Source follower design issue for cascoded two stage op-amp

    Why? The center voltage vo1 should be around VDD/2 (to achieve high swing), so you need that high shift 'cause VSG6 shouldn't get too much overdrive voltage. You can adjust Id6 by its W/L(6) ratio -...
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    Closed: Re: Relating Transmitter dBm to uV/m and EIRP

    14dBm ≙ 25mW, which generates 1.12V @ 50Ω - nearly your stated value.
  11. Closed: Re: Rail to rail input folded operational amplifier

    Depends. I used it for supply voltages of 1.0±0.2V and it worked well, as the Vth voltages of the process suited fine. With higher VDD this simple (but admittedly very elegant, because of its perfect...
  12. Closed: Re: Source follower design issue for cascoded two stage op-amp

    Ok, I see what you mean.


    Did I say that? I wrote weird terminology!
  13. Closed: Re: Why BJT is used for voltage reference and not CMOS

    Actually such a current source produces a PTAT voltage reference, which - by comparison with a second PTAT voltage reference - can be converted into a CTAT current reference.

    A MOSFET can be used...
  14. Closed: Re: Rail to rail input folded operational amplifier

    By W/L ratio (=1) between (P3,P4):(P1,P2) and (N3,N4):(N1,N2) resp. Don't forget: V2 & V3 must be supplied externally. Also, the common drain voltage of P5,N5 (≈VDD/2) supplies all the gates of N3,N4...
  15. Closed: Re: Source follower design issue for cascoded two stage op-amp

    No. The shift of the source follower MT1 of course is VSG (VSG1T in this weird terminology).
  16. Closed: Re: Calibre LVS Extraction Report Warnings Question.

    No, I wouldn't think so.

    The warnings just inform that the power PATHCHK couldn't be performed because of unattached power labels and ports. So the electrical - not the physical! - connectivity...
  17. Closed: Re: In snapback mechanism how voltage reduces when parasitic NPN is turned ON?

    Once the n-p-n turns on means it is conducting and so presents a low resistance to the ESD event. Such an ESD event owns a certain energy E = ∫V(t)*I(t)dt , which is dissipated in that n-p-n...
  18. Closed: Re: Optimized MinCap, Minres values for 10 MHz amp simulation using Spectre

    Due to very probable serial connection of RC elements I'd calculate with the 10-fold frequency, hence 100MHz. So I'd try e.g. with mincap=100fF and minres=16Ω (f = 1/2πRC).
  19. [SOLVED]Closed: Re: Common mode gain simulation for differential amplifier using balun

    In order to stay consistent with Ken Kundert's Test Bench description, you should name the input balun Bi (i for input) and the output balun Bo (o for output).



    Yes, I think so!
  20. [SOLVED]Closed: Re: Common mode gain simulation for differential amplifier using balun

    I think the second paragraph of 3.1 Gain in the a.m. PDF should read (only for the Balun nomenclature of your a.m. picture!):

    To measure the common-mode gain, set the AC magnitude on Vic to 1 V...
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    Closed: Re: ConnectLib files in ams simulation Cadence

    Yes. You have to create your own level converter - if the AMS lib doesn't offer one.
  22. Closed: Re: What is Double Snapback Characteristics in High-Voltage nMOSFETs

    Snapback - in this context - means the sudden receding of the voltage at a certain current, which generates a kink (or a knee) in the I-V characteristic of the device.
  23. Closed: Re: What is the difference between LVS and ERC ?

    - LVS means Layout versus Schematic comparison
    - ERC means Electrical Rules' Check
    - DRC means layout Design Rules' Check

    These all are necessary checks with their own rules' sets. Depending on...
  24. Closed: Re: How to change the m factor (multiplication factor) for Instances in cadence

    Depends on how you want the multiplication be done:

    Either m equal instances of the same device, then instantiate this device <1:m> times in parallel. Or you can multiply it by its Number of...
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    Closed: Re: Current reference design for CS-DAC

    1) I think your wp/wn ratio is too large. Increase your nmos widths, keeping the original w/l ratios.

    2) If you decrease the above widths ratio by this method, you should be able to keep your pmos...
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