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Type: Posts; User: daskk62

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  1. Closed: Alternative of “can not set both range and type on function declaration” in verilog?

    I am writing a verilog code for calculation of variance, in my verilog code I am calling a definition file, the definition file is as follows

    but in the line function reg [MAXIMUM_FUNC_WIDTH-1:0]...
  2. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    Instead of `include "math.v" in the code, i just paste the contents of math.v in the bottom side of the verilog module. So, now in case verilog also it is not showing error, but,in the vivado...
  3. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    Thank you, everyone. Although, I have copied the data from the .v, verilog to .sv system verilog file and converted the design to system verilog based design. program run with XX as the output in...
  4. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    155476

    Please find the attachment, which includes all the codes.
  5. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    Thank you ads-ee for the reply, I am getting some errors like
    1) cannot set both range and type on function declaration
    2) root scope declaration is not allowed in verilog 95/2K mode
    I dont know...
  6. Closed: Facing some error in Verilog HDL coding of Standard deviation calculation?

    The standard deviation (SD, also represented by the lower case Greek letter sigma σ for the population standard deviation or the Latin letter s for the sample standard deviation) is a measure that is...
  7. Closed: My FPGA Basys 3 Board is not showing output?

    Actually I am working in an DSP alorithm, in the top module of my verilog code I called my data as given in attatched file. But when I am dumping bitstream in the FPGA Basys 3 kit ( LEDs as output)...
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