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Type: Posts; User: Junus2012

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  1. Closed: Re: How to generated different bit patterns in Cadence Virtuoso

    Dear friends,

    Thank you for your help
    Please forgive my stupid question, I am unable to invoke the vector file, how can I edit or call this file from my simulator.
    Thank you once again
  2. Closed: Re: How to generated different bit patterns in Cadence Virtuoso

    Dear Vivekroy

    Thank you for your nice help, I will check to see if my ADE simulator support the UltraSim simulator,
    meanwhile I read the article, it is very helpful and answer my demand,
    only...
  3. Closed: Re: Simulating digital part in ADE Cadence Virtuoso

    Thank you Boss for your reply,
    I am sorry to tell you I could not find the setting you are referring in your explanation, it would be very kind of you if you refer me to more details or picture...
  4. Closed: How to generated different bit patterns in Cadence Virtuoso

    Dear friends,

    I am designing full custom shallow register,
    to test my circuit I need clocks and different periodic bit stream, what is the appropriate signal source that support my test ?
    ...
  5. Closed: Simulating digital part in ADE Cadence Virtuoso

    Dear Friends,

    is it possible to use some part designed by Verilog or VHDL with other schematic circuits ?

    for example I designed a three bit digital counter and I want to put this counter with...
  6. Replies
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    Closed: Re: Verilog Coding in Cadence Vertuoso

    Thank you for your reply,

    I use the verilog to fast implement some digital part in my circuit before I customly build it with my technology.

    One question please, If I create a Verilog cell, is...
  7. Replies
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    Closed: Verilog Coding in Cadence Vertuoso

    I am using Cadence vertuoso IC6.1.5-64b

    It is the first time for me to write verilog in Cadence,

    I have created new cell view in one of my libraries. I selected the Verilog with HDL reading ...
  8. Closed: Re: Op-amp design specification for certain application

    Thank you guys for your help

    Now understand that if I want to work at some gain I should not follow exactly the formula of GBW as it, because it define the frequency at the value of -3dB or when...
  9. Closed: Re: Op-amp design specification for certain application

    Dear Barry

    Thank you for your reply

    indeed Ao is the problem, how can I still have high Ao of my operational amplifier at frequency of 1 MHz ??

    and by the way if I would follow the formula...
  10. Closed: Op-amp design specification for certain application

    Dear friends,

    if my application requires an amplifier that can amplify a signal with frequency of 1 MHz with variable adjustable gain from unity to 100. How much should be the Gain bandwidth...
  11. Closed: Re: CMRR is less than the DC differential gain

    Dear Dominik

    I have noticed in some cases that netlist from schematic is different from the netlist of layout, like changing the drain source positions,, how can I correct it for the LVS i mean...
  12. Closed: Re: CMRR is less than the DC differential gain

    Dear Fvm
    Dear friends

    in the last months when I was used to ask about the CMRR, I was just doing the schematic design, at that time I had very big value, then you told me that is ok because my...
  13. Closed: Re: CMRR is less than the DC differential gain

    Dear dominik

    In the transient simulation is giving near perfect results, however it is depending on the ampliftude of the applied signal, it is degrading as the input amplitude increasing.

    I am...
  14. Closed: Re: CMRR is less than the DC differential gain

    Dear friends,

    I have simulated the circuit with schematic view and give a reasonable value of CMRR.

    The problem is only at post layout simulation. As Frankrose has mentioned, I have a common...
  15. Closed: CMRR is less than the DC differential gain

    Hello friends,

    I am simulating the CMRR of my amplifier, I am getting the CMRR = 80 dB at DC frequency while the DC differential gain is 103 dB. My amplifier is fully differential amplifier,
    ...
  16. Closed: Re: layout connection using different metalization layers

    I have four available metal layers, which means M4 is the top layer
  17. Replies
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    Closed: Re: Port size in layout design

    Thank you for your kind answer,

    No I am confirmed that pin size has no affect on the electrical proparties of the circuit
  18. Closed: Re: PMOS WELL of same bulk potential of different transistor groups

    Dear friends,

    Thank you for your reply,

    I understand from your kind explanation that there is no difference in electrical proparties if I put them in the same or different well, I am talking...
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    Closed: Re: current mirror matching issue

    indeed most of the people are matching them in different groups, you can see the design problem 12.15 in the book of "The art of analog layout". Also in one of your suggestion in other post you have...
  20. Closed: Re: layout connection using different metalization layers

    Ok let me clear it again,

    you mean to say for the rails only one should use the top metal layer, but the routing is can be done as for other kind of signal connection,
  21. Closed: Re: layout connection using different metalization layers

    Dear Sam :D

    in my technology, the top metal layer Metal 4 has big via and contact width, therefore in my circuit I used metal 1 for the VDD and GND as any other connection, this is again a...
  22. Closed: PMOS WELL of same bulk potential of different transistor groups

    Dear friends,

    I have different PMOS matched transistors matched in different groups but all they have the same bulk potential (bulk connected to the VDD), if these groups are near to each other is...
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    Closed: Re: Port size in layout design

    Dear ljp,

    Thank you for your reply,

    Then why I see some people in youtube makes the port pin for VDD and GND very big ?
  24. Replies
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    Closed: Port size in layout design

    Dear friends,


    is there any rule that I should do the size of the port pin ? or it is just like a label and has no electrical proprieties or influence

    Thank you
  25. Closed: layout connection using different metalization layers

    Dear friends,

    I am using the CMOS technology from AMS. it supporting me with four metal layers. except metal 4, I have metal1 and metal 2 and metal 3 having the same via and contact Dimensions. my...
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