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Type: Posts; User: Dominik Przyborowski

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1. ## Thread: Understanding the inversion coefficient proposed by EKV

by Dominik Przyborowski
Replies
2
Views
402

### Closed: Re: Understanding the inversion coefficient proposed by EKV

Ad A. It is possible and using EKV in simulation is not necessary. However, you need to characterise transistors (simple dc sweep to get gm/Id curve and extractspecific current). The most common...
2. ## Thread: CMRR is less than the DC differential gain

by Dominik Przyborowski
Replies
10
Views
608

### Closed: Re: CMRR is less than the DC differential gain

Dc operating points for schematic and extracted views. What they are?

by Dominik Przyborowski
Replies
2
Views
456

### Closed: Re: Varactor C-V Curves In Cadence

The simplest way is to use ac analysis and measure imaginary part of current.
For a very low values of Vds and/or Vgs negative capacitance or asymmetrical (Cgs not equal to Csg) is nothing...
4. ## Thread: Rational Approximation of Gaussian LPF

by Dominik Przyborowski
Replies
6
Views
455

### [SOLVED]Closed: Re: Rational Approximation of Gaussian LPF

I have no idea what is used by ADS (i have not touched it even). As I mentioned, the only known for me case is an approximation of Hurwitz polynomials. The odd order polynomials has only complex...
5. ## Thread: CMRR is less than the DC differential gain

by Dominik Przyborowski
Replies
10
Views
608

### Closed: Re: CMRR is less than the DC differential gain

Compare the current consumption and dc levels between schematic and extract (I suppose you are using OA views, nor spf netlist - correct me if my assumption is wrong).
Generate device only...
6. ## Thread: CMRR is less than the DC differential gain

by Dominik Przyborowski
Replies
10
Views
608

### Closed: Re: CMRR is less than the DC differential gain

Transient simulations giving similar results? How you generates post-layout netlist?
7. ## Thread: measuring the parasitic capacitance at a certain node in cadence

by Dominik Przyborowski
Replies
7
Views
399

### [SOLVED]Closed: Re: measuring the parasitic capacitance at a certain node in cadence

What would you like to do?
1. Simulate capacitance at specific node?
2. Extract capacitance for all nodes?
3. Read parasitic capacitance from extracted view?
What views you have?
What tools...
8. ## Thread: measuring the parasitic capacitance at a certain node in cadence

by Dominik Przyborowski
Replies
7
Views
399

Yes, it is.
9. ## Thread: Installing Cadence , Assura , EXT and MMSIM in Ubuntu

by Dominik Przyborowski
Replies
3
Views
631

### Closed: Re: Installing Cadence , Assura , EXT and MMSIM in Ubuntu

In theory it can be installed on any Linux distribution.
In practice, the only blessed by Cadence is RHEL 6.
It means, on RHEL it works always, on other distros you need to know how to married them...
10. ## Thread: Rational Approximation of Gaussian LPF

by Dominik Przyborowski
Replies
6
Views
455

### [SOLVED]Closed: Re: Rational Approximation of Gaussian LPF

The quassi-gaussian filter (bandpass, with quassi-gaussian impuls response) is CR-(RC) ^n, and for n>4 is no big difference.
The mentioned by you Hurwitz approximation is the only one close to gauss...

by Dominik Przyborowski
Replies
19
Views
746

### Closed: Re: Adding a pulsed switch to a dc voltage source in cadence library

The author is so unclear...
What I have understood, the point here is to have square wave with 50MHz frequency, and levels between ground and vdd, while vdd is defined by another vdc source. This...

by Dominik Przyborowski
Replies
19
Views
746

### Closed: Re: Adding a pulsed switch to a dc voltage source in cadence library

It seems you try to do simple thing in very complicated way.
Describe once again what you would like to achieve. It can be graphical explanation too.
13. ## Thread: Drai and source via contact

by Dominik Przyborowski
Replies
1
Views
179

### Closed: Re: Drai and source via contact

Only poly is important.
14. ## Thread: Port size in layout design

by Dominik Przyborowski
Replies
4
Views
321

### Closed: Re: Port size in layout design

Various reasons. Visibility on large layouts, requirements for various tools, etc.
15. ## Thread: current mirror matching issue

by Dominik Przyborowski
Replies
7
Views
547

### Closed: Re: current mirror matching issue

The best option is to keep transistors in stack abutted. It makes layout the most compact in this case.
16. ## Thread: devideing large MOSFET gate using muti fingers

by Dominik Przyborowski
Replies
4
Views
338

17. ## Thread: Input transconductance relationship ti the differential or common mode voltage

by Dominik Przyborowski
Replies
7
Views
671

### Closed: Re: Input transconductance relationship ti the differential or common mode voltage

The first approximation is 1-tgh^2(vin/nVt), which is true for BJT and weak inversion. For general mosfet diff pair, it transconductance is described by derivative of non elementary Lambert W...
18. ## Thread: Post-layout Simulation Errors in Virtuoso with av_extracted view

by Dominik Przyborowski
Replies
1
Views
328

### Closed: Re: Post-layout Simulation Errors in Virtuoso with av_extracted view

You have 78 terminals but only 6 defined in the subcircuit. I don't have enough knowledge about verilog/vhdl, however define buses width explicite in the module definition.
19. ## Thread: Hot NWELL warning in layout design

by Dominik Przyborowski
Replies
6
Views
543

### Closed: Re: Hot NWELL warning in layout design

Yes, you can waive this warning
20. ## Thread: Frequency Divider Circuit issue

by Dominik Przyborowski
Replies
28
Views
2,944

### Closed: Re: Frequency Divider Circuit issue

Define initial conditions - your output start with undefined state. Add gmin or cmin to simulation (don't familiar with ltspice so I don't know how)
21. ## Thread: Matching of big array transistors

by Dominik Przyborowski
Replies
3
Views
584

### Closed: Re: Matching of big array transistors

Read papers about D/A Converters. There is a lot of stuff how to deal with layout effects for large number of matched transistors - both for dc like for high speed optimization.
22. ## Thread: Analog circuit design automated

by Dominik Przyborowski
Replies
3
Views
922

### Closed: Re: Analog circuit design automated

Look for similar events:
DAC session for ML/AI
23. ## Thread: [moved] Distribution of process and mismatch in ADE XL monte carlo analysis

by Dominik Przyborowski
Replies
1
Views
317

### Closed: Re: [moved] Distribution of process and mismatch in ADE XL monte carlo analysis

Distribution of quantity is defined in model file.
24. ## Thread: Layout versus Schematic layout design issue

by Dominik Przyborowski
Replies
8
Views
4,592

### Closed: Re: Layout versus Schematic layout design issue

So, you doing it wrong. Proper usage of device parameters is your friend. As I remember correctly, you are using AMS C35 process, so NF and M are interchanging and there are no LDE (as far as I...
25. ## Thread: Layout versus Schematic layout design issue

by Dominik Przyborowski
Replies
8
Views
4,592

### Closed: Re: Layout versus Schematic layout design issue

Of course it is and not only these features. The question is, whether you have an access to proper tools and/or licenses.

Using Virtuoso Layout XL/GXL there is a direct binding between nets and...
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