Type: Posts; User: wahab.khan

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  1. [SOLVED]Closed: Re: Need help creating Vivado Timing Constraint

    Have you tried
    get_pins -of_objects [your clock here] -filter [NAME =~ "b_comms.u_comms/u_pcie1/u_sync_pcie/*"]
    This will return all pins from a specific clock domain in the given instance.
  2. Replies

    Closed: Re: SPI communication in SDK

    I'm not sure what you mean. Doesn't the function provided by SDK check for completion of the transfer? If you're trying to check if the data was correctly written to the destination, then you'll have...
  3. Closed: Re: Using calculated CRC as seed for the next CRC calculation

    You'll achieve what you've asked in your post if you do what comment # 2 says, but you'll probably also need to implement some logic to check if the last slab of data has been received and then reset...
  4. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    Also, the zip file you've attached doesn't contain source files. They seem to be located outside the vivado project folder.
  5. Closed: Re: CDC - How make merge data after conversion?

    You will have data skew because 240 MHz is not a multiple of 100 MHz, so for some input samples you will have two output samples and for some you will have three output samples. If you want to...
  6. Closed: Re: CDC - How make merge data after conversion?

    Like ads-ee said, you need to upsample your data. With your current design FIFO will always empty faster than it is filled. Why not get rid of the FIFO and just use flip-flops to synchronize data...
  7. Replies

    Closed: Re: Inferred VHDL dual port RAM template

    You could add an if-else condition on the assignment to "q" such that if read and write address are equal and write enable is also '1', then "q" should be assigned "data", else it should be assigned...
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