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Type: Posts; User: pragash

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  1. Replies
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    Closed: Re: Buck converter vs buck-boost converter

    thank you so much for the answer. any equation for efficiency or current draw in the Buck, Boost and buck-Boost converter? i will help me to understand the power loss even better. thanks.
  2. Replies
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    570

    Closed: Buck converter vs buck-boost converter

    which one is more power efficient? Buck converter or buck-boost converter?

    some of you may say its depends on your application. if lets say i can use either one. which one will be more power...
  3. Closed: Re: Battery cutoff voltage vs 0% battery voltage

    hi Klaus,
    thank you for the link. i have never seen it before. i reading it right now.

    apart from that, i would like to get some advice from your experience/embedded system design practice.
  4. Closed: Battery cutoff voltage vs 0% battery voltage

    i have a battery which has:
    maximum voltage : 4.35V
    cut-off discharge voltage: 3V

    i want to know what is the voltage which my product should be in 0% battery. is it 3V? Are we supposed to...
  5. Closed: Re: Regulator strategy - embedded system power design

    4.35V is charge voltage. I believe it is also the maximum voltage of the battery after charging. I'm not interested in high efficiency in charging mode.

    - - - Updated - - -


    i agree. thanks...
  6. Closed: Regulator strategy - embedded system power design

    i have a battery which has:
    maximum voltage : 4.35V
    cut-off discharge voltage: 3V

    my MCU voltage range is 1.8V to 3.8V. what is the best switching regulator i can employ for the minimum loss? i...
  7. Replies
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    Closed: Re: will crystal oscillator draw current?

    thanks for elaborate explanation FvM
  8. Replies
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    372

    Closed: Will crystal oscillator draw current?

    im using a crystal oscillator in my embedded system design. i wonder if crystals draw current. if yes , how much?

    i have attached datasheet of the crystal im using here.
    ...
  9. Closed: Re: Impact of parasitic capacitance and parastic inductance on DC and crystal oscilla

    Dear KlausST, refer back to my earlier question, do we need to reduce parasitic capacitance and inductance on the DC supply line of the PA, LNA and Osc ? the DC supply lines are placed closed to RF...
  10. Closed: [CST] How to simulate a layout to know the potential EMI/EMC issue

    I know that CST can simulate PCB layout to predict EMC/EMI issue which will the product fail radiated spurious emission test at certification. can anyone tell me how to do it? any document with...
  11. Closed: Re: Impact of parasitic capacitance and parastic inductance on DC and crystal oscilla

    yes, DC power supply of an AC circuit such as PA, LNA Osc and etc.
  12. Closed: Impact of parasitic capacitance and parastic inductance on DC and crystal oscillator

    we know that we need to avoid parasitic capacitance (electric field) and parasitic inductance (magnetic field) on the RF/Microwave circuit layout. My question is, how about the DC layout and the low...
  13. Closed: TRL calibration kit for PNA series (E8358A)

    i have fabricated TRL calibration kits for my design. however, i figured that it's not straight forward to do TRL calibration in the PNA E8358A. we need to add new calibration kit before using them...
  14. Closed: Re: [CST] How to simulate Radiated Spurious Emissions (RSE)

    i would like to predict radiated spurious emission test failure via EMC/EMI simulation.
  15. Closed: [CST] How to simulate Radiated Spurious Emissions (RSE)

    i know there is a way to simulate radiated spurious emissions using CST. can anyone have methodology documents or know how to do it step by step?
  16. Closed: [ADS] ADS simulation not using graphic card memory

    im doing momentum or EM simulation in ADS. however, my graphic card memory is not used in the simulation. that graphics card is stated in ADS simulation acceleration and full fill the acceleration...
  17. Closed: Re: [ADS]method to establish correlation between LNA EM simulation and circuit simula

    I was looking for a methodology to optimize the circuit with parasitics. thanks for your input. I really appreciate it.
  18. Closed: Re: [ADS]method to establish correlation between LNA EM simulation and circuit simula

    I got what you mean now. actually, the layout follows good RF layout guidelines which avoid long interconnects and parallel ground plane underneath component pads and so on. However, parasitic...
  19. Closed: Re: [ADS]method to establish correlation between LNA EM simulation and circuit simula

    could you please explain this further? are you asking to measure parasitic inductance and capacitance of the each transmission line?
  20. Closed: [ADS]method to establish correlation between LNA EM simulation and circuit simulation

    it's often easy to design an LNA circuit by doing impedance matching using "Smith chart utility" tool in ADS. In the layout simulation, due to parasitic introduced by the layout, the layout...
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    Closed: Re: [ADS] ADS netlist error

    sorry, solved the problem myself. the goal which i set to optimize impedance looking into port 1 is wrong. i set wrong experssion in the goal. i set complex impedance at 1st which is the mistake....
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    Closed: [ADS] ADS netlist error

    154128

    netlist error above appearing on my Momentum simulation. Please let me know how to solve it. thanks.
  23. Closed: Re: How to make cluster computer with MSI desktop and MSI laptop

    Any idea for that kind of software?
  24. Closed: How to make cluster computer with MSI desktop and MSI laptop

    i have MSI WT72 laptop and a desktop which uses X99A XPOWER AC (MS-7881) mother board. How can interface both computers and make cluster computer?

    Note: Thunderbolt 3 (USB-C) is only available in...
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    Closed: Re: need 7pF to 10pF at 2.5GHz

    Hi ktr,
    looks like you are stuck. the basic rule of thumb is design an interconnect which does not introduce parasitic inductance to the design. since you have already designed it, you are trying to...
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