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  1. Closed: Re: Strategy for a multi signal generator using a MAX10

    Hello!



    I think it will happen gradually and naturally.

    Now I don't even fully understand the FPGA related vocabulary. It doesn't mean that I have
    to learn it first. For instance, I'm not...
  2. Closed: Re: Strategy for a multi signal generator using a MAX10

    Hello!

    Thanks for your advice.
    I'm aware I may be doing a lot of things the wrong way, but that's the point: I'm doing things and
    I get them working.
    I don't know exactly how high I score on...
  3. Closed: Re: Strategy for a multi signal generator using a MAX10

    Hello everybody!

    Just to keep you informed. I have tested one of the 3 strategies I was thinking about (the 3rd one,
    using shorter wave sets with double access ram, and interpolate the results)....
  4. Closed: Re: Strategy for a multi signal generator using a MAX10

    Hello!

    Thanks for your reply!



    Yes, that's what I just found out. I'm thinking of using a dual port RAM as if it was a single one, and therefore hope to
    have access to 2 samples on the same...
  5. Closed: Re: Strategy for a multi signal generator using a MAX10

    Hello!

    You're right. Sorry. I was referring to this discussion.

    In the meantime, I made error calculations to estimate what would be a reasonable amount of lookup table to
    store a sine wave....
  6. Closed: Strategy for a multi signal generator using a MAX10

    Hello!


    As explained in another post, I'm trying to make a multichannel signal generator.
    At the moment, it works fine with sine waves, which is quite boring, but at least
    it works. The...
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Many thanks for all your support and detailed replies.
    By going to the basics (led blinker, but using a submodule to divide the clock), I found out
    what was wrong in my code. I needed...
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Thanks for your mail!
    I'm getting closer, this time it compiled. Now I would need some explanation.
    Here is the whole code. So I used the contextual menu to get a template. Now from
    my...
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Thanks for your reply!
    I tried to do something... But I don't understand the compilation errors.
    Just in case, I took your code although mine was basically the same.
    See attached...
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Thanks for your reply.
    The MAX10 I'm using is MAX10M50DAF484C8G.
    One of the largest.
    I'm looking for a verilog method to specify that I want to use the internal RAM.
    Currently looking...
  11. Replies
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Thanks for your reply.



    I'm aware this might be a tricky subject. But although it cannot really be compared, writing
    in a CPU flash can be tricky. But it can be done, and for example...
  12. Replies
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Thanks for your reply.



    Not necessarily a problem with my code (it works) but a problem in the way I declare the array
    and on the way I initialize it. When it compiles (i.e. when the...
  13. Replies
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Thanks for the explanation.
    Ok for the formatting. I didn't know I could put comments in the middle of the definition.
    In fact, doing that way does not take more space because the...
  14. Replies
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    Closed: Re: About Separating Supplies on PCB.

    Hello!

    Thanks for your reply. OK, that's a good input. In the meantime, I have made measurements, and also
    a comparison between a Tek signal generator and the hardware I made.
    NB: I'm comparing...
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    Closed: Re: About Separating Supplies on PCB.

    Hello!



    I'm not sure of what you mean by different time. I am hooking my scope's ch1 and ch2 on outp and outn,
    then use a math function of the scope to calculate the difference, so on the math...
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    Closed: Re: About Separating Supplies on PCB.

    Hello!

    Thanks for your replies.



    OK, that's a good start point. On top of that, Klaus was saying that voltage noise is current noise x impedance, so if
    I get a solid plane, the impedance...
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    Closed: About Separating Supplies on PCB.

    Hello!


    I'm not sure this is the proper place for that kind of question, so if it's not,
    @moderators: please feel free to move this post.
    I have made my first FPGA design. I'm using a MAX10...
  18. Closed: Re: Verilog: read 2 values from an array at the same time.

    Hello!

    Thanks for your reply!
    And for the solution! It was really a silly question. Indeed, I was incrementing at every step.
    It works now.

    By the way, I have asked a few times, but how can...
  19. Closed: Re: Verilog: read 2 values from an array at the same time.

    Hello!

    Thanks for your replies.
    In the meantime, I tried, and could have the result I wanted.
    I made a table of 1024 16-bit values:
    reg[15:0] sine[1023:0];
    Then I made a script to fill them...
  20. Closed: Verilog: read 2 values from an array at the same time.

    Hello!

    I have successfully made a first version of a signal generator, and now I would like to make it dual channel.
    If I make an arbitrary signal table, and want to read it from 2 different...
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    Closed: Re: How to instantiate a submodule in Verilog

    Hello!

    Thanks for so many replies while I was sleeping!
    I changed div_clk to wire, and it compiled at once. Thanks a lot!

    I also changed the instantiation by using .clk_out(div_clk) and it...
  22. Replies
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    Closed: How to instantiate a submodule in Verilog

    Hello!

    I'm using Quartus with Verilog. I have made a design that works, but as it becomes bigger everyday,
    I have to start splitting it into modules.
    Now I have been reading books about verilog...
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    Closed: Re: Hints for pin assignment

    Hello!

    Thanks for your reply.
    In my example, the 28 pins are supposed to be useful. The 16 bit bus is fully used, the2 input and output SPI engines are fully used.
    And let's admint that the...
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    Closed: Re: Hints for pin assignment

    Hello!

    Thanks for your reply.
    I'm aware that this top module is not like a program. So back to my question:
    If I'm doing a hardware (or let's say a hardware equivalent) of a chip that has 28...
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    Closed: Re: Hints for pin assignment

    Hello!

    Thanks for your reply.
    Post 8 said "In general modern FPGAs and their tools are quite flexible and forgiving in terms of routing.", which doesn't reply
    clearly to my question.
    Now if you...
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