Search:

Type: Posts; User: Shady Ahmed

Page 1 of 4 1 2 3 4

Search: Search took 0.02 seconds.

  1. Closed: Fully differential continuous time integrator

    Hello, I am designing an integrator of a continuous time sigma delta ADC using a fully differential amplifier on cadence with input freq 1.5MHz and sampling freq at the comparator 256MHz.
    In the...
  2. Replies
    1
    Views
    2,956

    Closed: [Moved]: Verilog A code for Timer

    Hello,

    I am trying to write verilog-A code to model a circuit that acts as an analog timer.
    By default, the output is High, when it receives start signal (positive edge), the output should be low...
  3. Replies
    2
    Views
    674

    Closed: Power Management References

    Dear All,
    I am studying a course about DC DC converters its types and control loops and battery chargers.. But I am confused and need a good reference and/or tutorials and/or courses. I know about...
  4. Closed: Re: Low Dropout Regulator Power Supply Rejection

    Thanks for ur input.
    At first I thought that the pass MOS width would have an effect on the PSR but it turned out it didn't.

    Now i simulated the LDO PSR using some ideal components to know what...
  5. Closed: Low Dropout Regulator Power Supply Rejection

    Hi all,

    I am designing a low drop out regulator, with the specifications of power supply rejection of -30 dB up to 10 MHz, with load current 2mA.
    Using 0.13um technology and 1.8v Supply.
    With 1V...
  6. Closed: Common Mode Feedback for 2 stage difference differential Amplifier

    I am designing a difference differential amplifier following the attached schematic. With a folded cascode first stage & Common Source as a second stage.
    ...
  7. Closed: Decimation Filter for a Sigma Delta ADC

    I have been working in the design of a 3rd order sigma delta analog to digital converter. right now I am concerned with the implementation of the digital part, the digital filter & the decimation...
  8. Replies
    2
    Views
    1,153

    Closed: Op amp Common Mode Feedback Design

    I am designing a 2 stage fully differential amplifier, however I don't fully understand the CMFB circuits and how should I design it.

    Also, the relation between the gain of the CMFB circuit versus...
  9. [SOLVED]Closed: [Moved]: Continuous Sigma Delta ADC coefficients (Schreier Tool Box)

    I am designing a 3rd order Continuous time ADC , with 1 MHz Bandwidth ,32 OSR and 3 level Comparator.

    I have a question regarding the coefficient values.

    I used the equation:
    coefficient * fs...
  10. Closed: [Moved]: Sigma Delta ADC Linearity & 3rd Harmonic

    I am working on a 3rd order, 1 MHz Sigma Delta ADC with the following Specs
    3 level quantizer and OSR = 32.

    I am facing a linearity problem that i don't know how to fix it.
    The system achieved...
  11. Closed: Re: Question about Components in Cadence

    Thanks for the answer, I knew it had to be in cadence but needed a name for that feature, I'll look into it.
  12. Closed: [Moved]: Question about Components in Cadence

    I have a question in Cadence,
    say for example that i created a component (op amps ) and i intend to use that component in another schematic, for instance : i'll place it 10 times, however i want to...
  13. Closed: Re: Continuous Time Sigma Delta ADC Integrators

    The op amp Gain Bandwidth is supposed to be 200 MHz , so i think it should have been able to catch up with the step response with 64MHz frequency, maybe 60 degree phase margin is little too much ? or...
  14. Closed: Re: Continuous Time Sigma Delta ADC Integrators

    I went back to the op amp and performed a step response with a unity gain amplifier setup.
    shown in the next figure the test bench schematic:
    119732

    shown in the next one, the DM stb analysis of...
  15. Closed: Re: Continuous Time Sigma Delta ADC Integrators

    The output ranges of the integrators in the transient simulation of the ADC are manageable and can be tolerated by the op amps swings.



    I designed several op amps with Phase margin ranging...
  16. Closed: [Moved]: Continuous Time Sigma Delta ADC Integrators

    I am designing a 3rd order sigma delta ADC with OSR = 32 , Fsampling = 64 MHz, with 1.5 bit comparator. The design is in 0.13um technology.

    The target peak SNR from the system design (i used...
  17. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    No, i didn't change anything else, i just removed the CMFB from the schematic, and simulated with the following schematic shown in the figure (by adding resistors followed by source of 0.6V)
    119309...
  18. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    Here are the modified schematic along with the new bode plots, it looks the same.
    119252

    119253
  19. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    No, i am not sure that the CMFB part is the culprit.



    Do u mean to compensate the CMFB detector? (i.e : add capacitors in parallel with the R_CMFB?)



    Ok, i think at this point it'd be...
  20. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    I understand that theoretically, the loop has positive gain, however, when i was designing the op-amp, i spent a lot of time connecting the inputs to the vcvs the other way, and it didn't work at...
  21. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    Here u can find the op-amp schematic.
    119191
  22. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    any help ? The op amp with the ideal vcvs in the CMFB circuit still affects the Sigma Delta ADC performance greatly!! I just want to make sure it works before consuming time designing the real CMFB...
  23. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    Do u mean replacing the op-amp (the error amplifier) with the differential one stage amp??
    Because i read about some CMFB architectures (check the images for examples)
    118988

    and i wasn't sure...
  24. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    I think this maybe due to the CMFB circuit,, and since i'll have to implement real CMFB circuits anyway, i started looking into CMFB circuits architectures.
    Any specific architectures for 2 stage...
  25. Replies
    18
    Views
    1,756

    Closed: Re: Sigma Delta ADC Integrators

    I simulated the ADC and plotted the output of the comparator (D1 , D0, D_1) , and the integrator outputs.
    I can't quite get where the problem come from

    118757118758118759118760118761118762

    ...
Results 1 to 25 of 86
Page 1 of 4 1 2 3 4