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Type: Posts; User: pragash

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  1. Closed: Re: CST -Computer Simulation Technology for Microstrip Antenna Design

    The efficiency, surface current, power flow, farfields are the outcome of field monitoring you insert in the simulation.
  2. Closed: [Solidworks] Parametric conical helix antenna on a dielectric

    im stuck half way of construction of parametric conical helix antenna on a dieletric. i have created intersection line but struggling to make it a planar surface on top of the conical object as shown...
  3. Closed: [CST] Antenna import from Solidworks to CST

    I draw "conical helix antenna on a dielectric sheet" in AutoCAD. I labelled the layers of the helix as layer 1 and cone as layer 2.

    And then import the drawing from AutoCAD to Solidworks. The...
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    Closed: Re: drawing meander line helix in CST

    what software shall i use? Autocad or Solidworks? any example of meander line helix creation?
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    Closed: drawing meander line helix in CST

    i know that it is not possible to draw meander line helix in CST. how shall i draw parameterized meanderline helix to be imported to CST for simulation and optimization?

    Please refer to the...
  6. Closed: 20GHz to 40GHz circuit implementation method

    I would like to know the RF circuit implementation method for 20GHz to 40GHz. The RF circuits are LNA, filters and PAs. Can these circuits implemented on a PCB or only IC? Any particular IC...
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    Closed: Re: Buck converter vs buck-boost converter

    based on my understanding, treez answer is makes the most sense.

    question: buck-boost regulator or buck regulator? which one is more efficient

    Treez's answer: we need to see the regulator...
  8. Closed: Re: Battery cutoff voltage vs 0% battery voltage

    what u mean by depends on the battery? battery type/chemistry? we are using lithium polymer battery.
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    Closed: Re: Buck converter vs buck-boost converter

    thank you so much for the answer. any equation for efficiency or current draw in the Buck, Boost and buck-Boost converter? i will help me to understand the power loss even better. thanks.
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    Closed: Buck converter vs buck-boost converter

    which one is more power efficient? Buck converter or buck-boost converter?

    some of you may say its depends on your application. if lets say i can use either one. which one will be more power...
  11. Closed: Re: Battery cutoff voltage vs 0% battery voltage

    hi Klaus,
    thank you for the link. i have never seen it before. i reading it right now.

    apart from that, i would like to get some advice from your experience/embedded system design practice.
  12. Closed: Battery cutoff voltage vs 0% battery voltage

    i have a battery which has:
    maximum voltage : 4.35V
    cut-off discharge voltage: 3V

    i want to know what is the voltage which my product should be in 0% battery. is it 3V? Are we supposed to...
  13. Closed: Re: Regulator strategy - embedded system power design

    4.35V is charge voltage. I believe it is also the maximum voltage of the battery after charging. I'm not interested in high efficiency in charging mode.

    - - - Updated - - -


    i agree. thanks...
  14. Closed: Regulator strategy - embedded system power design

    i have a battery which has:
    maximum voltage : 4.35V
    cut-off discharge voltage: 3V

    my MCU voltage range is 1.8V to 3.8V. what is the best switching regulator i can employ for the minimum loss? i...
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    Closed: Re: will crystal oscillator draw current?

    thanks for elaborate explanation FvM
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    Closed: Will crystal oscillator draw current?

    im using a crystal oscillator in my embedded system design. i wonder if crystals draw current. if yes , how much?

    i have attached datasheet of the crystal im using here.
    ...
  17. Closed: Re: Impact of parasitic capacitance and parastic inductance on DC and crystal oscilla

    Dear KlausST, refer back to my earlier question, do we need to reduce parasitic capacitance and inductance on the DC supply line of the PA, LNA and Osc ? the DC supply lines are placed closed to RF...
  18. Closed: [CST] How to simulate a layout to know the potential EMI/EMC issue

    I know that CST can simulate PCB layout to predict EMC/EMI issue which will the product fail radiated spurious emission test at certification. can anyone tell me how to do it? any document with...
  19. Closed: Re: Impact of parasitic capacitance and parastic inductance on DC and crystal oscilla

    yes, DC power supply of an AC circuit such as PA, LNA Osc and etc.
  20. Closed: Impact of parasitic capacitance and parastic inductance on DC and crystal oscillator

    we know that we need to avoid parasitic capacitance (electric field) and parasitic inductance (magnetic field) on the RF/Microwave circuit layout. My question is, how about the DC layout and the low...
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    Closed: TRL calibration kit for PNA series (E8358A)

    i have fabricated TRL calibration kits for my design. however, i figured that it's not straight forward to do TRL calibration in the PNA E8358A. we need to add new calibration kit before using them...
  22. Closed: Re: [CST] How to simulate Radiated Spurious Emissions (RSE)

    i would like to predict radiated spurious emission test failure via EMC/EMI simulation.
  23. Closed: [CST] How to simulate Radiated Spurious Emissions (RSE)

    i know there is a way to simulate radiated spurious emissions using CST. can anyone have methodology documents or know how to do it step by step?
  24. Closed: [ADS] ADS simulation not using graphic card memory

    im doing momentum or EM simulation in ADS. however, my graphic card memory is not used in the simulation. that graphics card is stated in ADS simulation acceleration and full fill the acceleration...
  25. Closed: Re: [ADS]method to establish correlation between LNA EM simulation and circuit simula

    I was looking for a methodology to optimize the circuit with parasitics. thanks for your input. I really appreciate it.
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