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Type: Posts; User: barry

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  1. Replies
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    Closed: Re: Solder paste stencil for internal layers

    Maybe, just maybe, you should tell us what software you are using. Showing a picture of the dialog for selecting layer colors is useless. Maybe you need to check "pastemask_top" and...
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    Closed: Re: 820 1K - what does the 1K mean?

    Why do you say: "The 820 of course tells me the value of the res"? Maybe the 820 tells you reference designator and 1K is actually the value. Maybe "820 1K" is the range of acceptable resistors. I've...
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    Closed: Re: Usage of Synchronous and Asynchronuos FIFOs

    It’s not just the clock speed that’s important. Are the clocks SYNCHRONOUS or ASYNCHRONOUS to each other?
    Asynchronous FIFOs are more complex.
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    Closed: Re: ADC output bit rate and PCB layout

    That seems correct.
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    [SOLVED]Closed: Re: Generation of 4 Phase Shifted clock Signals

    What kind of system would you have that requires a clock, but doesn't want to use digital logic?
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    [SOLVED]Closed: Re: Generation of 4 Phase Shifted clock Signals

    Use an FPGA. Use a microprocessor. Use some resistors, capacitors and inductors.

    Perhaps if you asked a better question you would get a better answer. Like maybe some specifics of exactly what...
  7. Closed: Re: Detect the absence of sampled AC signal (from digital filter) in verilog

    If your signal has enough amplitude I would think that using the level detection method should be the easiest; noise shouldn't be an issue. What is your problem with the logic? Nothing could be...
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    Closed: Re: power supply residual voltage

    How are you testing this? How are you applying a "2KV surge"? How are you measuring it? What are its characteristics? Are you picking up something with your scope (or whatever you're using) rather...
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    Closed: Re: Implementation of ADC

    Read post #3 again. adsff explains how to use the digital elements of an FPGA to effect analog functions. But you can't "write program for analog part" in Verilog, but you can write the digital...
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    Closed: Re: Implementation of ADC

    You need more than Verilog code, you need analog circuitry to implement an ADC: comparators or opamps, etc. Unless your FPGA has those features, you're not going to be able to create an ADC.
  11. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    I don’t see how the example in #9 can load the ROM from the bit file; it uses a clock.
  12. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    I don't understand what you've got there. What is "rom_op" ? What is addr? Isn't that logic? How do you get data into a RAM without writing it? (To be honest, I don't actually know the mechanism of...
  13. Closed: Re: Film capacitor failed in flyback smps at high temperature?

    If you read the data sheet, you'll see that the operating frequency of the cap has a large impact on it. What's your frequency? What's your 'extreme' test temperature?
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    Closed: Re: Instrumentation AMP Virtual short.

    Yes, it's a virtual short. If you actually analyze the circuit, you'll see that as the IA open-loop gain goes to infinity, the voltage at the two inputs becomes the same.
  15. Closed: Re: Why are SMD components so much smaller than their THT versions?

    The die is the EXACT SAME SIZE for through-hole or SMT devices. The TH parts are bigger in order to acommodate the larger lead frame. You'll notice that SMT leads are much smaller than TH leads...
  16. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    Maybe just a minor point (depending on speed and utilization), but when it's implemented in the code, you now have to generate all the associated routing to handle writing. A ROM, by definition, does...
  17. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    If it's a ROM, can't you just define it as an IP block that gets loaded during configuration? For example, with the Xilinx tools you would have a memory defined that uses a .coe file that contains...
  18. Closed: Re: TPS54560: Voltage is dropping when load connected

    I can spot the mistake: those protoboards are TERRIBLE for the type of circuit you are playing with. Stray inductance, stray capacitance, etc. Usually, the manufacturer shows a recommended PCB...
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    Closed: Re: Data string length to be send out from FPGA

    1) Receive command "Read All"==>transmit all the data
    2) Receive command "Read Register X"==>transmit the data in Register X

    I really don't understand your question "which type of data string...
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    Closed: Re: Altium "has only one pin" error - why?

    You didn't split your bus out correctly. Look at this-"creating a Multichannel design": https://www.altium.com/documentation/18.0/display/ADES/((Multi-Sheet+and+Multi-Channel+Design))_AD
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    Closed: Re: Altium "has only one pin" error - why?

    On the top level AOUTR is a bus. On your schematic, it's a single signal.
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    Closed: Re: Altium "has only one pin" error - why?

    Without seeing the underlying schematic, audioinput.schdoc, it's impossible to tell.
  23. Closed: Re: Determine whether a binary number is of power of two in verilog code

    I told you it was early in the morning!
  24. Closed: Re: Determine whether a binary number is of power of two in verilog code

    Without thinking too hard early on a Monday morning, I think this could be done with a bunch of cascaded XORs. Output would be logic 1 if only one bit is set. Exception: is zero a power of 2?
  25. Closed: Re: Is a tantulum different from a microferet tantulum cap?

    I think you misheard. MICROFARAD, not “microferret”. And, there’s no such thing as a .68k cap. .68 microfarad, maybe? 68 microfarad?
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