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  1. Closed: Re: Car battery STARTER voltage help (not charger) using variety of methods (possibly

    It seems from looking at ebay that your cheapo SLA battery is for UPS or similar lower current applications, which translates to high internal resistance and low amperage for a starter motor...
  2. Closed: Re: Car battery STARTER voltage help (not charger) using variety of methods (possibly

    Probably a vehicle so heavily modified along with a starter motor solenoid that draws more current than the ignition switch is rated for.

    Given that 0 gauge copper cables run about 0.1 mOhm and...
  3. Closed: Re: Problem understanding Signed Fractional Format

    They use .996795654 for .996805 because you can't get closer to the actual value with only 15-bits. You would have to have an extra 4-bits minimum to obtain a result that is correct to the 6th...
  4. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    So what their management still hires new grads to "work" on F-ing up their models thinking they are "saving" money...(short memory problem or management turnover)

    Why did you edit all your source...
  5. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    No I wasn't talking about sformat, I was talking about a custom function I wrote to left justify an array


    Did you try the example in #8 it isn't the same as the first SV version as it uses a...
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    Closed: Re: verilog set parameter to a module

    The (* some_attribute = some_value *) are for synthesis attributes. Though in this case the attributes don't look like synthesis attributes, they must be custom attributes. They certainly don't show...
  7. Closed: Re: OV7670 camera interface with Digilent SPARTAN 3E

    Uhh...yes?

    If the part is too small you'll either have to get a different board than the starter board or have to sacrifice features/functions in the design until it fits, i.e. change the VHDL...
  8. Closed: Re: OV7670 camera interface with Digilent SPARTAN 3E

    From what I saw at a glance it looks like all the code is synthesizable behavioral RTL and should only require a new UCF file to assign the pins to the equivalent locations on the Digilent board.
    ...
  9. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    Then don't cross post to multiple sites or on this site.

    Cross posting is an inherently rude and selfish act that has no place on any forum, if you must cross post in the very first post you...
  10. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    You didn't have to use systemverilog it was just cleaner...
    Using only Verilog 2001 compatibility...

    module dir_path_verilog;

    // parameter [64*8-1:0] MY_PATH; // this results in a string with...
  11. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    The vlog command line probably requires an escape character on the / in the directory name, so it doesn't get interpreted as a directory separator.

    - - - Updated - - -

    Escape doesn't work.

    I...
  12. [SOLVED]Closed: Re: Verilog read-file task, unexpected behaviour

    I would just fgetc the first character and determine if you are looking at a comment line (#) a read or write line (r/w) and only parse the lines with an fscanf if the line is a r/w line. Right now...
  13. Closed: Re: CYPRESS FXLP & WVGA SENSOR in Snapshot Mode

    The cypress FX2LP is NOT a PLD, SPLD, GAL, CPLD, or an FPGA. It is a USB controller/microcontroller. This post was started in the wrong section, so I'm moving it to the microcontroller section where...
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    Closed: Re: Active-HDL VHDL simulation problem

    I would delete any work or other libraries that you've compiled your code into, then recompile the design into a work library and run your simulation again.

    I would suspect you have an old version...
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    Closed: Re: Detect long string signal

    Is your intention create an Analog design to tap off a differential signal to detect switching between 0 bps or 30 Mbps then the previous suggestions might work for you, but I suspect this is for the...
  16. Closed: Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Most FPGA's internal pullups are on the order of 50K-150K ohms and are there specifically to ensure the input buffers see a valid logic level instead of a floating pin. They are definitely not to be...
  17. Closed: Re: Delay a signal in a system verilog testbench using jaspergold

    the number after a # delay (i.e. in your case assign #0.5 ack_d = ack) means #(timeunit) if your testbench has a directive `timescale 1ns/1ps or a timeunit 1ns statement then your # delay should be...
  18. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    No I was just commenting on the fact that the core generated as a 1024 deep FIFO, which can be seen by looking at the .xci file contents.

    <spirit:configurableElementValue...
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    Closed: Re: SD Card not showing 4 GB

    Use option 3 from the following link:
    https://www.eassos.com/blog/how-to-remove-delete-partition-from-sd-card-on-windows-10/

    i.e. use diskpart in a command prompt window and select the volume you...
  20. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    That's odd, I posted yesterday about what the issue was but there isn't a post, must have forgot to click the post button.

    Anyway the problem is in your constant for Almost_Full_Depth:

    CONSTANT...
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    [SOLVED]Closed: Re: for generate with step other than one

    Just multiply the index, e.g. step size of 3 instead of 1

    my_loop: for i in 0 to 7 generate
    my_assignment(3*i) <= my_signal(3*i);
    end generate;
  22. Closed: Re: Misconceptions and flaws noticed by the more educated...

    Schmitt trigger had to fix the punchline you had "the scientist is all smiles".

    Personally I would tell the wizard to f**k off and walk straight across the room and chat her up (since I know the...
  23. Closed: Re: Crt tv - click sound turn off and i start again

    Gives the original meaning to a circuit with "bugs". Those cockroaches should have read betwixt's posts before working on the CRT, or using it as their "home".
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    Closed: Re: System verilog, fork join_any

    If you have tasks a, b, and c then if a takes 10, b task 2, and c takes 5 time units then the fork-join_any will exit when task b finishes (FYI a and c will still run to completion) and continue on...
  25. Closed: Re: PCB manufacturing by printing webs with a conductive material (school assignment)

    It looks like Voltera has a online store and the ink is $99 and it says it can print ~85 simple boards.

    They also have a "starter kit" that appears to come with ink, the printer, solder paste, and...
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