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    Closed: Re: Design compiler synthesis

    I assume some form of retiming took place.
  2. Closed: Re: How to load an already compiled design in Design Compiler?

    you need to reload the netlist, any constraints, corners, and all libraries.
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    Closed: Re: How to clock gate in hierarchy?

    Just instantiate the cell you want by hand. Tell synthesis not to touch it.
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    Closed: Re: How to clock gate in hierarchy?

    Sure, you can try to play with the CTS at block level, or even do some PSO if the block is really not going to operate for a long period of time. Can it be done? Absolutely. Especially if you have a...
  5. [SOLVED]Closed: Re: measuring the parasitic capacitance at a certain node in cadence

    Mandatory reminder that Cadence is a company. There is no tool called Cadence...
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    Closed: Re: How to clock gate in hierarchy?

    Logic synthesis tools and CTS are able to handle that automatically for you. Do not code or instantiate clock gating by hand.
  7. Closed: Re: Coverage improvement from AU.TC faults

    can you clarify what do you mean by 'tied cells'? are you referring to tie high/tie low cells?
  8. Closed: Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo

    I think the tool is having issues with outputting a log file. Make sure the folder has write permission set correctly. Make sure the logfile argument is being passed correctly.
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    Closed: Re: meaning of placeable cells

    I think you are referring to standard cells, but that is a pretty weird terminology.
  10. Closed: Re: How to ensure the accuracy of static timing analysis (STA) by using .lib

    you have to trust that the people that built the .lib file knew what they were doing. it's not only the number of points that matter, but also the range. I have seen a lot of 9x9 and 11x11 tables...
  11. Closed: Re: TimeDesign in innovus with value 0 of Shift Phase

    phase shift means that the path is from a negedge to a posedge, for instance, instead of the normal case where paths start at one phase and end at the same phase (posedge to posedge). phase shift !=...
  12. Closed: Re: layout connection using different metalization layers

    For routing power to the cells, it has to be done in M1 (the lowest metal). These are called rails. For distributing the power across the chip you will use rings and stripes, typically in the highest...
  13. Closed: Re: layout connection using different metalization layers

    you are confusing power rails with power routing (stripes, rings, trunks, etc.)
  14. Closed: Re: layout connection using different metalization layers

    isn't the top metal meant for power routing? that is pretty common.
  15. Closed: Re: Delay a signal in a system verilog testbench using jaspergold

    fix your assertion then.
  16. Closed: Re: Delay a signal in a system verilog testbench using jaspergold

    first things first... delay statements are not synthesizable and are rarely used. make sure you understand what is being asked of you. it is ok in a testbench, never in a design.

    second, you have...
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    Closed: Re: gate connection using poly vs metal

    You can't route with poly unless the technology is ~20 years old. It's a non-starter.
  18. [SOLVED]Closed: Re: Methodology to calculate the Clock Uncertainity values.

    someone will implement the top level clock tree and should be able to give you some estimates of how bad the clock distribution is. That is the skew. Margin is margin, extra timing that you put in...
  19. Closed: Re: InstallScape error when installing Cadence IC617

    that's why I suggested /tmp in the first place...
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    Closed: Re: XOR gate IC supply current

    Absolutely not. You can get static current that is beyond all specs if a pin is left floating. Have seen it time and time again.
  21. Closed: Re: Post synthesis simulation shows setup and hold time violations while DC doesn't

    Good enough for early on during synthesis, nowhere near enough to get a chip done.
  22. Closed: Re: Post synthesis simulation shows setup and hold time violations while DC doesn't

    Nope. You trust your STA and your LVS. Avoid gate-level simulations at all costs.
  23. Closed: Re: Overloading Arithmethic operators in Design Compiler

    You can create a workaround, but it will be mighty ugly. You should also look into using designware libraries for your big arithmetic operands intead of the +/* signs.
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    Closed: Re: if/else vs. if/if in combo logic

    Think of the structure of a mux gate (which tends to be used to implement if-like structures). There is no priority, S=0 or S=1, period. There is no notion of 'executed first'.
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    [SOLVED]Closed: Re: Code coverage of a design

    Code coverage is not about transitions, I think you are confusing the terminology.
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