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Type: Posts; User: vGoodtimes

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  1. Closed: Re: Output

    you always have pragma tricks for this as well.
    eg:


    constant kWhatever : std_logic :=
    -- synthesis translate_off
    'X' when true else
    -- synthesis translate_on
    '-';
  2. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    $sformat(my_str, "%s") means "place the result in my_str", the formatting is "%s", (error) the string to use to replace the first %s isn't provided.
  3. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    apparently you can use #sformat. I've never done this, so no idea if it actually works. either way, you can probably provide this to $display or such in order to see what prints out.
  4. Closed: Re: Error loop must terminate within 10,000 iterations (vhdl)

    how so? It is almost copied from examples in vivado's synthesis guide.

    --edit, it looks like altera/intel don't support textio for initialization while xilinx does. or at least as of two years...
  5. Closed: Re: Error loop must terminate within 10,000 iterations (vhdl)

    I think it wasn't intended to be a simulation testbench. To load a rom from a file in vhdl, I think you can use an impure function to initialize the memory in the declaration section. see...
  6. Closed: Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    you can try lowering the i2c clock rate. For testing, using something like 1khz-10khz might be fine.
  7. Closed: Re: I2c Master - when master SDA is in 'Z', sda bus does seem to go high.

    Go into details about the pull-up resistor strength and any level-shifting ic's between the devices. Also, does the design work at lower i2c clock rates. eg, 1/10th or 1/100th the normal rate.
    ...
  8. Closed: Re: Spread spectrum clock generator using dcdl

    @bubu_not_taken, For xilinx, look at the iodelay system. You don't get the 1:1 semantics you want, but you can adjust delays precisely and dynamically.

    also, your question is not well formed. ...
  9. Closed: Re: Spread spectrum clock generator using dcdl

    For xilinx FPGA's you would use the iodelay elements. They have control systems to reduce the impact of process/voltage/temperature changes. Altera/Intel likely have something similar.
  10. Closed: Re: Misconceptions and flaws noticed by the more educated...

    To the original topic, for me the issue was coursework trying to present concept after concept after concept while saving motivation for last. This makes a lot of sense for reference manuals, but...
  11. Closed: Re: Optimizing case statement with large input

    case statements in verilog are syntax sugar for the chained if-else statements. synthesis vendors either infer that one and only one case can be reached, or a pragma (fullcase/parallelcase) is used....
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    Closed: Re: if/else vs. if/if in combo logic

    for synthesis they are equivalent. For simulation I think there is a minor difference /wrt how always blocks using "out" get triggered. IIRC, style 2 can cause other always blocks to trigger when...
  13. Closed: Re: Vivado Taking A Long Time To Run Synthesis & Implementation

    I think he's asking a slightly different question that what's been answered. His problem is more similar to "how do you pipeline an IIR filter". The SHA512 computation has rounds where the output...
  14. Closed: Re: Vivado Taking A Long Time To Run Synthesis & Implementation

    Any pipeline latency appears in the longest feedback path due to the output of the 80-rounds being the init for the next chunk. Maybe pipelining would help for the immediate problem of synthesis...
  15. [SOLVED]Closed: Re: Problem with UART clock value in a VHDL sample code

    the decimal value is even, the hex value is odd.
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    Closed: Re: Ethernet speed - some basic questions

    @joniengr, symbol rate isn't the best term here. I think you are talking about useable data rates. I think some of the previous posts may be confusing because they focus on the media-dependent,...
  17. Closed: Re: Including VHDL libraries to add two signals

    Yes. It seems weird, but this works fine. std_logic_unsigned defines functions on std_logic_vector. There are no conflicts with numeric_std.
  18. Closed: Re: Including VHDL libraries to add two signals

    std_logic_unsigned gives std_logic_vector an unsigned interpretation. This is similar to Verilog. It works fine. The gotcha is that "0" = "00" now, while "0" /= "00" (+warning) before.
  19. Closed: Re: Including VHDL libraries to add two signals

    ieee.numeric_std.all; -- This is the official source for "unsigned" and "signed" types. Just use this. Monkeys on a ladder and whatnot.
    ieee.std_logic_arith.all -- This also defines "unsigned" and...
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    Closed: Re: VHDL modulo 2^64 addition

    The code shown looks correct for this problem. My guess is that one or more of the terms is incorrect.

    For any encryption core, you really need to get detailed test vectors. Not just input and...
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    Closed: Re: VHDL modulo 2^64 addition

    please give an example of inputs-outputs giving a wrong value.
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    Closed: Re: VHDL modulo 2^64 addition

    make a(i) 64 bits.
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    Closed: Re: [moved] Inferring latches issue

    Does this really sound like students?


    it does look like the design has unregistered outputs. Although it isn't clear if that was part of the spec. If so, two-process gets a little more...
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    Closed: Re: [moved] Inferring latches issue

    x, y are also combinatorial loops because they are in the combinatorial process.



    process (CLK)
    begin
    if rising_edge (CLK) then
    PS <= FS; -- good, but there should be a reset
    -- x...
  25. Closed: Re: HDMI in and out , just connected in to out.

    Are there problems with lower resolutions?
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