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Type: Posts; User: jeetesh

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  1. Replies
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    Closed: Re: Use generic in package: VHDL

    Thank you FvM and TrickyDicky. I know generic is not needed in my example, but I want to use this in some other designs. That was just an example, not design.

    TrickyDicky, I got it. Thanks for...
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    Closed: Re: Use generic in package: VHDL

    Thank you FvM for your reply. We can design this like you did, but can we pass generic value to a package. If yes, then how? Considering this example.
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    Closed: Use generic in package: VHDL

    I have defined a generic in entity and I want to pass it to package. How to do this, without using component and others. I read somewhere that VHDL-2008 provides this feature. But I don't know how to...
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    Closed: Re: Verilog Error!! Please help me...

    It is again showing same error while viewing RTL Schematics.. @yourcheers
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    Closed: Verilog Error!! Please help me...

    I am getting an error at the udp instantiation line, while viewing RTL schematic, as: Unsupported Switch or User Defined Primitive
    but syntex is correct.... help me.. I am using xilinkx 14.1
    ...
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    Closed: Re: Verilog Error!! Please help..

    thank u.... I was doing the same silly mistake....
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    Closed: Verilog Error!! Please help..

    I am getting an error as while designing an OAI22 in verilog(Xilinkx ISE 14.1) : ERROR:HDLCompilers:26 - "OAI21.v" line 26 expecting 'endmodule', found 'if'
    21: module OAI21(a, b, cntrl, z);
    22:...
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