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  1. Replies
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    [SOLVED]Closed: Re: Folded cascode output resistance

    Thanks frankrose. It is perfect. Now as VBP2 decreases, (VSG-|Vt|) of M7 increases and with the same current, VSD of M7 decreases. This means an increase in VSD of M5 which pushes it more into...
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    951

    [SOLVED]Closed: Re: Folded cascode output resistance

    Thank you guys for your answers.
    Vivek Roy, you are right. I am workng in submicron.
    frankrose, the transistor is at the border of saturation or somehow in triode region so the gds formula should...
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    [SOLVED]Closed: Folded cascode output resistance

    Hi all,
    I have a folded cascode opamp with NMOS differential input and the current is steered in PMOS cascode.
    The output conductance of all transistors should be theoritically abreviated as
    gds=...
  4. [SOLVED]Closed: Re: What's the difference between stacked and cascode configurations?

    Great explanation dick_freebird.
    I would summarise by saying, cascode is a common gate (Vbias cascode and RF gnd) and in stacked the gate is connected to Vbias through R and to gnd via a capacitor...
  5. Closed: Re: How to optimize all transistors' size (length and width) in Cadence software?

    I am sorry to say this but you should not. If you are unable to understand where to start a differential amplifier using hand calculations, you are not qualified to be an analogue design engineer. I...
  6. Closed: Re: Reliability question for a casode 3.3V buffer using 1.8V MOS.

    In my experience, the foundry will never state the maximum voltage stress. In power amplifier, the drain to source voltage usually reaches 2 Vdd (for a single transistor). As a rule of thumb, you can...
  7. Closed: Re: TSMC 0.18um CMOS Tech - Question on Maturity

    Hi. For question 1 I think your answer is right.
    For 2, I think they update the library every while. Since you are going to fabricate with them, it should be available to you. You will need a non...
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    Closed: Re: Effective width of pmos and nmos in series

    So as an abbreviation, let us say that Wp= 2Wn as Kp=Kn/2 to have equal speed and equal resistance transistors.
    So to have one Wp, you should have two series of (2Wp). If it is one PMOS and one...
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    1,673

    Closed: Re: Effective width of pmos and nmos in series

    Hi smita. In order to answer your question, it is important ti know the gate voltages of the transistors (a,b,c). Is it a logic circuit or analogue circuit?
  10. Closed: Re: DC Load Line for single stage CMOS amplifer

    I think the idea of drawing the load line is to estimate the optimum load to achieve (for example) maximum efficiency while keeping the output linear in a power amplifier.
    In my opinion the load...
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    Closed: Re: Calculating transit frequency of mosfet

    Hi. ft depends on the biasing current (DC current from drain to source). it is theoritically gm/Cgs where gm depends on the square root of Idc
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    Closed: Re: Technology node and min channel length

    Technology node is the minimum available channel length in the process. 40 nm node means 40 nm transistor length available (may be only digital transistor)
    65 nm means 65 nm length. If they have 60...
  13. Closed: Re: How come differential cascode structures affect on PA characteristics?

    Hi. As I said above, do not rely too much on their info. I have wasted long times understand or reproduce their designs. In my opinion, they have this performance and they do not have a good...
  14. Closed: Re: How come differential cascode structures affect on PA characteristics?

    Hi. In which frequency is this paper? what do you mean by mmW? 5 GHz or 100 GHz? It is important to know.
    I have read many of this professors PA papers and I can say with comfort that they do not...
  15. Closed: Re: Need suggestion tools/flow to check reliability issue during power loss

    If I understand correctly your question, I think Apache Redhawk is the one.
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    Closed: Re: Understanding sigma delta ADC

    Hi Chinmaye,
    I would try to explain more. Now assume you have an audio signal which is 20 kHz bandwidth and the basic Nyquist rate is 48 kHz (a typical value used in audio slightly higher than...
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    Closed: Re: VLSI job market in Middle East

    Hello again MNBahr,
    I am not completely aware with the market in Egypt, but I think there is some layout opportunities in SysDSoft, Silicon vision and other companies.
    In the UK, most companies...
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    Closed: Re: VLSI job market in Middle East

    Even I don't think I have the answers, but what are you waiting for? shoot your questions
  19. Closed: Re: 3-terminal capacitor in CMOS process : vncap vs vncap_inh

    The process is XFAB. If the capacitor has only 2 terminals in the layout and LVS is OK. What can be wrong if the capacitor substrate (in schematic) is floating?
  20. Closed: Re: 3-terminal capacitor in CMOS process : vncap vs vncap_inh

    Thank you jimito for your reply
    In my process, the schematic has 3 terminals. In layout two terminals and I have to create PD_C to connect the substrate.
    Now I have another question, If I left the...
  21. Closed: Re: 3-terminal capacitor in CMOS process : vncap vs vncap_inh

    I didnt get it. If I have three terminals capacitor and want to connect 2 terminals together (and not to GND).
    Is this possible? You said in another post that it is possible.
  22. Closed: Re: 3-terminal capacitor in CMOS process : vncap vs vncap_inh

    I have a problem here in 3-terminal capacitors. If I connect the bulk to terminal 2 for example and this terminal is not connected to GND I will get multiple stamped connection problem.
    Also I have...
  23. Closed: Re: [HELP] Elab error with Cadence ams(spectre) using VHDL netlist

    guys, I have the first problem also in my design. Could anyone help?
  24. Closed: Re: 3-terminal capacitor in CMOS process : vncap vs vncap_inh

    Hi fellows,

    I have one question regarding the same problem. If the capacitor has 3 terminal T1, T2, and suIs there any harm in connecting the capacitor substrate to T2 for example?

    The reason...
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    Closed: Re: How to use PDK in cadence

    Guys,

    Could someone advise how to set the CDSDIR? I mean which directory should it be?

    I go to tkit directory and try to run the command but have the following error "command not found"
    ...
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